Erasmus Langer
Siegfried Selberherr
Oskar Baumgartner
Markus Bina
Hajdin Ceric
Johann Cervenka
Raffaele Coppeta
Lado Filipovic
Lidija Filipovic
Wolfgang Gös
Klaus-Tibor Grasser
Hossein Karamitaheri
Hans Kosina
Hiwa Mahmoudi
Alexander Makarov
Mahdi Moradinasab
Mihail Nedjalkov
Neophytos Neophytou
Roberto Orio
Dmitry Osintsev
Mahdi Pourfath
Florian Rudolf
Franz Schanovsky
Anderson Singulani
Zlatan Stanojevic
Viktor Sverdlov
Stanislav Tyaginov
Michael Waltl
Josef Weinbub
Yannick Wimmer
Thomas Windbacher
Wolfhard Zisser

Hajdin Ceric
Assistant Prof. Dipl.-Ing. Dr.techn.
Hajdin Ceric was born in Sarajevo, Bosnia and Herzegovina, in 1970. He studied electrical engineering at the Electrotechnical Faculty of the University of Sarajevo and the Technische Universität Wien, where he received the degree of Diplomingenieur in 2000. In June 2000, he joined the Institute for Microelectronics, where he received the doctoral degree in technical sciences in 2005 and where he is currently employed as a post-doctoral researcher. His scientific interests include interconnect and process simulation.

Reliability of Interconnect Structures in 3D ICs

For the realization of modern 3D (Integrated Circuits) ICs new interconnect structures, such as through-silicon-vias and solder bumps, together with complex multi-level 3D ICs are gaining importance.
In the development of electronics packaging the principal aims are to lower cost, increase the packaging density, and improve performance while still maintaining or even improving the reliability of an integrated circuit. The application of new structures and materials inevitably introduces new reliability issues. The interconnect reliability is affected by degradation processes induced by thermal gradients, electromigration, and stressmigration.
Due to new technologies and ongoing miniaturization, the impact of the microstructure, which defines material properties and residual stresses in a metallic interconnect structure, gains importance. The systematic reliability study of interconnects in 3D stacked chips is currently not available. The reliability assessment of specific components of 3D interconnects and whole chips demands development of new TCAD methods and their utilization in combination with experimental reliability tests. The focus of our work is the development of models and simulation tools applicable to the most urgent reliability issues of modern 3D interconnects. Application of new materials and material compounds makes a multi-level modeling approach a necessity. The study of material properties demands approaches on the atomistic and microstructural levels. Within the scope of our research, the influence of the technology process conditions on microstructure and the residual stress in interconnects are studied and included in the overall analysis.
A wide spectrum of physical models and numerical methods is applied starting with ab initio calculations and molecular dynamics simulations at the lowest level. For a reliability study of interconnect components, such as through-silicon-vias and solder bumps, continuum mechanics and electromigration models are used and simulations based on the finite element method are carried out.

Electromigration-induced voiding in solder bump.

Home | Activities | Staff | Publications | Sponsors | Music | Contact Us