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7.2 Interaction of hydrogen with degradation and recovery dynamics

In the previous section it has been demonstrated that the recovery rate is independent of the hydrogen budget within the gate oxide. This is a strong indication that the oxygen vacancy is the responsible precursor for (math image). The following subsections study the time evolution and the energetic distribution of recoverable and quasi-permanent damage. Experiments are performed on selected hydrogen split wafers.

7.2.1 Energetic distribution and dynamic evolution of recoverable oxide traps

In this subsection, the energetic distribution and dynamics of the recoverable component is investigated in detail for three selected split wafers with different power-metalization and hydrogen budget within the gate oxide [186]. The applied technique is the ‘incremental sweep technique’ demonstrated in Subsection 6.3.3 [174].

During BEOL processing, titanium layers of different thicknesses were incorporated below the metalization in order to control the hydrogen diffusion from the upper hydrogen rich SNIT layer toward the gate oxide during fabrication. Titanium is known to be an effective barrier against hydrogen diffusion [187]. Hence, it is assumed that wafers with thick titanium barriers have less hydrogen within the gate oxide than wafers with thin titanium barriers. In this study three selected split wafers which provide vastly (about an order of magnitude) different hydrogen concentrations within the gate oxide are analyzed. This is demonstrated in Fig. 7.4 by the considerably different virgin CP characteristics.

Figure 7.4:  CP currents of the selected split wafers measured before stress at -60 °C. CP setup: \( V_\mathrm {GB} \) = \( 2.0\,\mathrm {V} \); \( f \) = 1\( \,\mathrm {MHz} \); rising/falling slopes \( \mathrm {6.4}\,\mathrm {V/\mu s} \). (a) Wafer \( \mathrm {\#1} \) (SM6P/30/H1) has a thin titanium bar- rier and a standard power-metalization (PM 1). (b) Wafer \( \mathrm {\#2} \) (SM6P/30/H2) has a similar thin tita- nium barrier as wafer \( \mathrm {\#1} \) but a different power-metalization (PM 2). (c) Wafer \( \mathrm {\#3} \) (SM6P/30/H3) has a thick titanium bar- rier and a standard power-metalization (PM 1). Wafer \( \mathrm {\#1} \) and Wafer \( \mathrm {\#2} \) have initially a much lower CP signal than Wafer \( \mathrm {\#3} \), suggesting a better passivated interface.

Wafer \( \mathrm {\#1} \) (SM6P/30/H1) and wafer \( \mathrm {\#2} \) (SM6P/30/H2) are supposed to have a well passivated interface (thin Ti liner \( \longrightarrow   \) much hydrogen \( \longrightarrow   \) low CP signal) while wafer \( \mathrm {\#3} \) (SM6P/30/H3) has a weakly passivated interface (thick Ti liner \( \longrightarrow   \) few hydrogen \( \longrightarrow \) high CP signal). In the following, different PMOS devices of the selected split wafers were stressed for 10/100/1,000/10,000\( \,\mathrm {s} \) at 125 °C.

After each stress run, degradation was quenched to -60 °C and the devices were analyzed using the ‘incremental sweep’ technique, cf. Subsection 6.3.3. The outcome includes (i) the time dependent recovery rates within the first 100\( \,\mathrm {s} \) (\( B_\mathrm {R} \)) after the termination of stress, (ii) the recoverable oxide trap profiles extracted from the incremental sweep (\( D_\mathrm {OX}^\mathrm {rec} \)), (iii) the quasi-permanent (math image) shifts (\( \Delta V_\mathrm {TH}^\mathrm {perm} \)) and (iv) the CP currents measured at the end of each characterization run (\( \Delta I_\mathrm {CP} \)). The results are illustrated for increasing stress times in Fig. 7.5.

Figure 7.5:  (a) Recoverable oxide trap profiles (\( D_\mathrm {OX}^\mathrm {rec} \)) of the selected split wafers recorded after different stress times. All samples show two peaks of similar amplitude and shape; the first is located close to midgap and almost fully developed after ten seconds of stress; the second is located in the upper half of the silicon bandgap and develops gradually as a function of stress time. (b) The recovery rates (\( B_\mathrm {R} \)) of the selected split wafers recorded within the 100\( \,\mathrm {s} \) constant gate bias phase (-1.5\( \,\mathrm {V} \)) directly post stress. All samples show similar time dependent recovery rates of approximately \( 1.9 \pm 0.2\,\mathrm {mV/dec} \). (c1) The quasi-permanent \( V_\mathrm {TH} \) shift (\( \Delta V_\mathrm {TH}^\mathrm {perm} \)) and (c2) the increase in CP current (\( \Delta I_\mathrm {CP} \)) of all samples as a function of stress time. Wafer \( \mathrm {\#1} \) shows a considerable higher quasi-permanent \( V_\mathrm {TH} \) shift than \( \mathrm {\#2} \) and \( \mathrm {\#3} \). The CP currents in (c2) correlate with the quasi-permanent \( V_\mathrm {TH} \) shifts in (c1) by a universal multiplica- tive factor. \( \Delta V_\mathrm {TH}^\mathrm {perm} \) and \( \Delta I_\mathrm {CP} \) show a power-law-like increase with stress time (fit lines), wafer \( \mathrm {\#1} \) having a larger power-law exponent than wafer \( \mathrm {\#2} \) and wafer \( \mathrm {\#3} \) (\( n_\mathrm {perm}^\mathrm {\#1} \) = 0.27; \( n_\mathrm {perm}^\mathrm {\#2} \) = 0.25; \( n_\mathrm {perm}^\mathrm {\#3} \) = 0.19).

The effective density of state profiles of all split wafers are illustrated in Fig. 7.5 (a). All samples show very similar recoverable DOS profiles indicating that the trap precursor is actually independent of hydrogen, consistent with the results gained from the alternative wafer split discussed in Section 7.1. The measured recovery rates during the first 100\( \,\mathrm {s} \) constant gate bias phase are illustrated in Fig. 7.5 (b). In agreement with the DOS profiles, all samples show similar recovery rates of \( 1.9 \pm 0.2\,\mathrm {mV/dec} \) which slightly increase with stress time. On closer inspection of the energetic profile (\( D_\mathrm {OX}^\mathrm {rec} \)) two characteristic peaks emerge; the first one is located near midgap and is almost fully developed after ten seconds of stress; the second one is located in the upper half of the silicon bandgap and develops gradually with further increasing stress times. The quasi-permanent (math image) shifts (\( \Delta V_\mathrm {TH}^\mathrm {perm} \); measured for 100\( \,\mathrm {s} \) directly after the sweep procedure at -1.5\( \,\mathrm {V} \)) and the increase in the CP current (\( \Delta I_\mathrm {CP} \); measured directly after \( \Delta V_\mathrm {TH}^\mathrm {perm} \) by gate pulsing) are illustrated in Fig. 7.5 (c1) and (c2) as a function of the stress time. \( V_\mathrm {TH}^\mathrm {perm} \) and \( \Delta I_\mathrm {CP} \) correlate by a multiplicative factor consistent with previous results. The quasi-permanent damage is considerably larger for wafer \( \mathrm {\#1} \) (well passivated interface) than for wafer \( \mathrm {\#3} \) (weakly passivated interface) indicating that both components are directly linked to each other and to hydrogen. An exception is found in wafer \( \mathrm {\#2} \) (equipped with a different power-metalization PM 2) which has a similar ‘zero hour’ CP signal as wafer \( \mathrm {\#1} \) (cf. Fig. 7.4) and hence a comparably passivated interface but shows considerably less quasi-permanent damage. Except for the metalization, wafer \( \mathrm {\#1} \) was identically fabricated as wafer \( \mathrm {\#2} \). The quasi-permanent damage follows a power-law-like increase for all tested structures, the value of the exponent, however, increases proportionally to the hydrogen budget within the gate oxide.

In this subsection the density of state profiles of recoverable oxide traps was analyzed by making use of the ‘incremental sweep’ technique. In particular, two peaks located energetically in the middle and in the upper half of the silicon bandgap were investigated. By comparing three PMOS devices taken from selected split wafers, recovery was found to be independent of the hydrogen budget and the metalization process while the increase in the CP current and the quasi-permanent (math image) shift is strongly connected to the BEOL fabrication.

7.2.2 Interaction of hydrogen with recoverable and quasi-permanent damage

Two selected hydrogen split wafers (wafer \( \mathrm {\#1} \) (SM6P/30/H1) and wafer \( \mathrm {\#3} \) (SM6P/30/H3)) were subjected to a particularly designed experimental procedure in order to separate time and bias dependent recoverable damage from apparently quasi-permanent degradation, which is assumed to consist of interface states and locked-in oxide charges, cf. Fig. 6.27. Wafer \( \mathrm {\#1} \) has a thin Ti barrier and hence a lot of hydrogen within the gate oxide while wafer \( \mathrm {\#3} \) has a thick Ti barrier and hence a worse passivated interface. This is demonstrated by the considerably different initial CP currents and the different hydrogen signals detected with TOFSIMS, cf. Fig. 7.6 (a), and (b), respectively. Both wafers were fabricated with a standard power-metalization (PM 1).

The TOFSIMS image in Fig. 7.6 (b) shows the sub-metal BEOL layer stack of the two selected split wafers. Displayed are the oxygen and the titanium signals for the orientation within the BEOL stack. Underneath the Ti liners considerably different hydrogen concentrations are measured for wafer \( \mathrm {\#1} \) and \( \mathrm {\#3} \) in the post metal dielectric (PMD), the gate-poly and the gate oxide (GOX). In perfect agreement with the TOFSIMS results we obtain in Fig. 7.6 (a) that the initial CP signal of wafer \( \mathrm {\#1} \) (0.3\( \,\mathrm {nA} \)) is about 30 times lower than the ‘zero hour’ CP signal of wafer \( \mathrm {\#3} \) (9.0\( \,\mathrm {nA} \)). This is consistent with the assumption that the interface of wafer \( \mathrm {\#1} \) (\( D_\mathrm {it} \) = 2.3\( \times   \)10\( ^\mathrm {9} \) eV\( ^\mathrm {-1} \) cm\( ^\mathrm {-2} \)) is more efficiently passivated with hydrogen than the interface of wafer \( \mathrm {\#3} \) (\( D_\mathrm {it} \) = 6.9\( \times   \)10\( ^\mathrm {9} \) eV\( ^\mathrm {-1} \) cm\( ^\mathrm {-2} \)). The CP currents were recorded at a temperature of 50 °C using a pulsing frequency of 500\( \,\mathrm {kHz} \) and rising/falling slopes of 10\( \,\mathrm {V/\mu s} \), scanning roughly 500\( \,\mathrm {meV} \) of the silicon bandgap around midgap.

Figure 7.6:  (a) CP currents of the BEOL process split wafers \( \mathrm {\#1} \) (diamonds) and \( \mathrm {\#3} \) (triangles). Due to the higher hydrogen concentration within the gate oxide, wafer \( \mathrm {\#1} \) has a more efficiently passivated interface and a lower CP signal than wafer \( \mathrm {\#3} \). (b) TOFSIMS images of wafers \( \mathrm {\#1} \) and \( \mathrm {\#3} \). By modifying the titanium layer thick- ness, the hydrogen budget within the post metal dielectric (PMD), the gate-poly and within the gate oxide (GOX) can be controlled. Wafer \( \mathrm {\#1} \) has a thinner Ti layer than wafer \( \mathrm {\#3} \) and hence a higher hydrogen concentra- tion within the layers below, in particular, within the GOX.

The characterization procedure following NBTS (200 °C; 7.0\( \,\mathrm {MV/cm} \)) for a defined stress time ((math image)) is illustrated in Fig. 7.7 (a). By making use of the in-situ polyheater technique, the recovery phase can be performed at a much lower characterization temperature of 50 °C which decelerates thermodynamical recovery mechanisms and improves the charge pumping measurement resolution (degradation quenching).

After stress, the characterization procedure is initiated by a 1,000\( \,\mathrm {s} \) lasting recovery phase at -2.0\( \,\mathrm {V} \) (t\( _\mathrm {R1} \)). The relative amount of (math image) recovery during t\( _\mathrm {R1} \) between the first measured point after removal of the stress bias (40\( \,\mathrm {ms} \) post stress) and the last measured point (1,000\( \,\mathrm {s} \) post stress) is denoted as the time dependent recovery contribution (\( \Delta V_\mathrm {TH}^\mathrm {time} \)). Subsequently to t\( _\mathrm {R1} \), the gate bias is ramped down in 20\( \,\mathrm {mV} \) steps from strong inversion (-2.0\( \,\mathrm {V} \)) toward depletion (0.0\( \,\mathrm {V} \)) (S\( _\mathrm {D1} \)). In parallel, the (math image) shift is monitored as a function of the gate bias. One full gate bias ramp takes approximately 10\( \,\mathrm {s} \). Approaching depletion, the Fermi level moves from the valance band edge toward the conduction band edge, thereby gradually changing the ratio of free holes and electrons at the interface. After staying for 10\( \,\mathrm {s} \) at 0.0\( \,\mathrm {V} \) (t\( _\mathrm {wait1} \)), the gate bias is ramped back to -2.0\( \,\mathrm {V} \) (S\( _\mathrm {U1} \)). The difference in the (math image) shift recorded at -2.0\( \,\mathrm {V} \) at the beginning of S\( _\mathrm {D1} \) and at the end of S\( _\mathrm {U1} \) is denoted as the bias-dependent recovery contribution (\( \Delta V_\mathrm {TH}^\mathrm {bias} \)). After the first ramp down-up cycle, the maximum CP current is recorded for 10\( \,\mathrm {s} \) by pulsing the gate junction between strong inversion (-2.0\( \,\mathrm {V} \)) and accumulation (+1.0\( \,\mathrm {V} \)) at a frequency of 500\( \,\mathrm {kHz} \) (t\( _\mathrm {CP} \)). In the analysis, the maximum CP signal is converted into an interface state dependent threshold voltage shift (\( \Delta V_\mathrm {TH}^\mathrm {it} \)) by assuming an amphoteric nature of interface traps [89] and a flat density of state profile [37], cf. Subsection 2.2.2. After the CP cycle, a short 10\( \,\mathrm {s} \) lasting constant gate bias phase at -2.0\( \,\mathrm {V} \) (t\( _\mathrm {R2} \)) is performed followed by a second down-up ramp (S\( _\mathrm {D2} \); t\( _\mathrm {wait2} \); S\( _\mathrm {U2} \)). This basic MSM procedure is repeated six times on both devices of the wafer split with increasing stress times (math image) (1/10/100/1,000/10,000/100,000\( \,\mathrm {s} \)).

Figure 7.7:  (a) Basic MSM procedure used for degradation and recovery analysis. During stress, the polyheater tool is used to generate an elevated stress temperature of 200 °C. During recovery, gate bias sweeps and CP measurements are performed in order to monitor time and bias dependent \( V_\mathrm {TH} \) recovery and interface state creation. (b) The individual \( V_\mathrm {TH} \) shifts recorded at 50 °C after six subsequent stress runs (1/10/100/1,000/10,000/100,000\( \,\mathrm {s} \)): (b) wafer \( \mathrm {\#1} \); (c) wafer \( \mathrm {\#3} \). The time dependent \( V_\mathrm {TH} \) recovery (\( \Delta V_\mathrm {TH}^\mathrm {time} \)) is recored at a constant gate bias of -2.0\( \,\mathrm {V} \) directly post stress for 1,000\( \,\mathrm {s} \) (t\( _\mathrm {R1} \)). The bias dependent \( V_\mathrm {TH} \) recovery component (\( \Delta V_\mathrm {TH}^\mathrm {bias} \)) is the differ- ence in the \( V_\mathrm {TH} \) shift between S\( _\mathrm {D1} \) and S\( _\mathrm {U1} \) recorded at -2.0\( \,\mathrm {V} \). After S\( _\mathrm {U1} \), the maximum CP current is recorded for 10\( \,\mathrm {s} \) (t\( _\mathrm {CP} \)) and changes in \( I_\mathrm {CP}^\mathrm {max} \) are converted into cor- responding interface state dependent \( V_\mathrm {TH} \) shifts (\( \Delta V_\mathrm {TH}^\mathrm {it} \)). After gate puls- ing, the remaining \( V_\mathrm {TH} \) shift is considered to be quasi-permanent (\( \Delta V_\mathrm {TH}^\mathrm {perm} \)) since it is con- stant and independent of time and bias within the scope of the experiment, cf. t\( _\mathrm {R2} \), S\( _\mathrm {D2} \) and S\( _\mathrm {U2} \) in (b) and (c).

The (math image) shifts measured during the different stages of the experiment are illustrated for wafer \( \mathrm {\#1} \) (thin Ti/high H) in Fig. 7.7 (b) and for wafer \( \mathrm {\#3} \) (thick Ti/low H) in Fig. 7.7 (c). Shown are six curves corresponding to the six subsequent stress runs. In Fig. 7.8, the individual (math image) shifts are depicted separately for both wafers as a function of the stress time.

Figure 7.8:  The individual \( V_\mathrm {TH} \) shifts depicted for both wafers as a func- tion of stress time: (a1) \( \Delta V_\mathrm {TH}^\mathrm {time} \); (a2) \( \Delta V_\mathrm {TH}^\mathrm {bias} \); (b1) \( \Delta V_\mathrm {TH}^\mathrm {it} \) and (b2) \( \Delta V_\mathrm {TH}^\mathrm {perm} \). \( \Delta V_\mathrm {TH}^\mathrm {time} \) and \( \Delta V_\mathrm {TH}^\mathrm {bias} \) show a log-like evolution with stress time and their contribution is similar for both split wafers. \( \Delta V_\mathrm {TH}^\mathrm {it} \) and \( \Delta V_\mathrm {TH}^\mathrm {perm} \) follow a power- law-like evolution with stress time and scale by a factor 3. The weakly passivated wafer \( \mathrm {\#3} \) provides considerably lower interface and quasi-permanent damage than the well passivated wafer \( \mathrm {\#1} \). Furthermore, the well passivated wafer \( \mathrm {\#1} \) provides larger power-law exponents (\( n_\mathrm {perm}^\mathrm {\#1} \) = 0.30; \( n_\mathrm {it}^\mathrm {\#1} \) = 0.29) than the weakly passivated wafer \( \mathrm {\#3} \) (\( n_\mathrm {perm}^\mathrm {\#3} \) = 0.23; \( n_\mathrm {it}^\mathrm {\#3} \) = 0.22).

The following characteristics are obtained: (i) within the initial 1,000\( \,\mathrm {s} \) constant bias phase in strong inversion (-2.0\( \,\mathrm {V} \)), a similar amount of time dependent recovery (\( \Delta V_\mathrm {TH}^\mathrm {time} \)) is obtained for both H-levels, cf. Fig. 7.8 (a1); (ii) the total (math image) shift decreases during S\( _\mathrm {D1} \) and increases during S\( _\mathrm {U1} \), cf. Fig. 7.7 (b) and (c); (iii) a significant bias dependent reduction in the (math image) shift is observed after S\( _\mathrm {U1} \) which is again similar for both H-levels, cf. Fig. 7.8 (a2); (iv) after the intermediate CP cycle, the remaining degradation level is quasi-permanent and cannot be reduced further by an additional gate bias ramp toward 0.0\( \,\mathrm {V} \), cf. Fig. 7.7 (b) and (c); (v) The remaining quasi-permanent (math image) shift (\( \Delta V_\mathrm {TH}^\mathrm {perm} \)) and the interface state dependent (math image) shift (\( \Delta V_\mathrm {TH}^\mathrm {it} \)) are much larger for wafer \( \mathrm {\#1} \) than for wafer \( \mathrm {\#3} \), cf. Fig. 7.8 (b1) and (b2); (vi) the interface state dependent (math image) shift is smaller than the quasi-permanent (math image) shift but scales with \( \Delta V_\mathrm {TH}^\mathrm {perm} \) when multiplying \( \Delta V_\mathrm {TH}^\mathrm {it} \) by a factor 3; (vii) The power-law exponents (\( n_\mathrm {perm} \) and \( n_\mathrm {it} \)) are larger for wafer \( \mathrm {\#1} \) than for wafer \( \mathrm {\#3} \) causing faster degradation of the well passivated sample.

These seven findings on the bias and time dependence of the recovery, on interface state creation and on quasi-permanent damage, as a function of the H budget within the gate oxide, represent a comprehensive collection of NBTI characteristics. In the following, the single statements are cross-checked against our microscopic model presented in Fig. 6.27.

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