4.5.2.1 DMOSFET Structure

The DMOS structure is formed in SiC using a double ion implantation with two separate implantation masks. In this simulation we consider two n-type 4H- and 6H-SiC device structures fabricated on the same wafer and conditions. Both have a 10-$\mu$m thick n- drift layer doped at 1.7$\times$10$^{16}$ cm$^{-3}$. The p-type (boron) junction depth is predicted by simulation to be 0.9 $\mu$m formed with a box profile implant of 2$\times$18 cm$^{-3}$. In a real device, activation of the implants that form the p base regions requires annealing at temperatures in excess of 1500$~^{\circ}$C. Depending on the precise annealing conditions (time, temperature, and ambient), this anneal can create surface roughness through a process called step bunching [76]. Therefore, for this simulation analysis the channel mobility is set to 85 cm$^2$/V$\cdot$s [181] which is $\sim$10% of the bulk mobility, and a very reasonable value for channels in ion implanted base regions in SiC.

Figure 4.23: Cross section of DMOS power transistor in SiC.

The n+ (nitrogen) implants at the source contact are selected to have junction depth of 0.3 $\mu$m with doping concentration of 1.0$\times$10$^{19}$ cm$^{-3}$. The gate oxide thickness and the channel length are optimized to be 50nm and 1.5$\mu$m, respectively, for the desired on-state and off-state operation. Table 4.5 summarizes the parameters used for the simulation.

Table 4.5: Summary of optimized device parameters used for the simulation of a vertical DMOSFET.

parameter	value
gate oxide thickness and channel length	50 nm, $1.5\,\mathrm{\mu}$m
drift layer thickness and concentration	$10\,\mathrm{\mu}$m, 1.7 $\times10^{16}$ cm $^{-3}$
p-base thickness, length and concentration	$0.9\,\mathrm{\mu}$m, $6.5\,\mathrm{\mu}$m, $6.0\times10^{16}$ cm$^{-3}$
n+ source thickness, length and concentration	$0.3\,\mathrm{\mu}$m, $4.0\,\mathrm{\mu}$m, $1.0\times10^{19}$ cm$^{-3}$

T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation