4.5.3.2 ACCUFET Simulation

The simulation were performed in two steps. First the simulator was calibrated to obtain the desired on-state and off-state operation performance of the conventional lateral DMOSFET. For the calibration the dimensions of the experimental device obtained from [185,186] are used to define the simulated device. Once good agreement is obtained six parameters that alter the device performance of the accumulation-mode structure have been investigated as summarized in Table 4.6: The doping concentration of the n-drift region; the depth and the concentration of the implanted p-well; the doping concentration and the thickness of the n-channel (accumulation-layer); and the gate oxide overlap length. The p-well region has a Gaussian profile buried between 0.3 and 1.0 $\mu$m, which has to be optimized because it determines the thickness of the accumulation-layer region which in turn affects the gate oxide field, breakdown voltage, and on-resistance.

Table 4.6: Summary of optimized device parameters used for the simulation of an accumulation-mode lateral DMOSFET.

parameter	value
cell pitch (source-drain spacing)	$33\,\mathrm{\mu}$m
drift layer thickness and concentration	$10\,\mathrm{\mu}$m, 5.0 $\times10^{15}$ cm $^{-3}$
n- channel thickness and concentration	$0.3\,\mathrm{\mu}$m, $1.0\times10^{16}$
p-base thickness and concentration	$0.5\,\mathrm{\mu}$m, $1.0\times10^{18}$ cm$^{-3}$
gate oxide thickness and length	50 nm, $6\,\mathrm{\mu}$m

For the desired breakdown voltage of $1500\,\mathrm{V}$, the structure is optimized to have a $33\,\mathrm{\mu m}$ cell pitch, a $10\,\mathrm{\mu m}$ thick n-drift region doped at 5.0 $\times10^{15}\,\mathrm{cm}^{-3}$ and an n+ polysilicon gate electrode with a $50\,\mathrm{nm}$ thick gate oxide. When the buried p-base depth is larger, the built-in potential is unable to fully deplete the n-channel which causes high leakage currents. Therefore, its depth and implanted peak concentration of $0.5\,\mathrm{\mu m}$ (between $0.3-0.8\,\mathrm{\mu m}$) and 1.0 $\times10^{18}\,\mathrm{cm}^{-3}$ are predicted to give the optimum accumulation layer thickness at which the criterion for the device optimization (FOM) peak, as shown in Fig. 4.32 (left). The gate oxide overlap was varied from 4 to $7\,\mathrm{\mu m}$, and its influence on the surface field and operating voltage was analyzed. Simulation predicted that a gate oxide overlap length of $6\,\mathrm{\mu m}$ is optimum.

The accumulation-mode lateral DMOSFET shows a fairly large advantage in terms of electrical performance compared to its standard inversion-mode lateral DMOSFET counter part.

Figure 4.32: Effect of the accumulation layer thickness on device figure of merit (left), and comparison of transfer characteristics at room temperature for accumulation- and inversion-mode lateral DMOSFET (right).

The simulated transfer characteristics for both accumulation-mode and its counterpart inversion-mode lateral DMOSFET is depicted in Fig. 4.32 (right).

Figure 4.33: Forward biased characteristics at room temperature in 6H-SiC accumulation- and inversion-mode lateral DMOSFET.

Significant improvement on the reduction of the gate bias voltage (a logic level gate bias of $5\,\mathrm{V}$) has been achieved to obtain good on-state conduction. The device is normally off with a threshold voltage of only $3\,\mathrm{V}$ compared to that of $6\,\mathrm{V}$ for the inversion-mode structure.

Excellent IV characteristics were obtained with good current saturation and gate control as depicted in Fig. 4.33. In addition to its superiority in the logic level gate bias voltage operation, the new structure has also shown significant improvement on the higher gate bias voltage characteristics.

One of the important areas of improvement for the SiC MOSFET device is the decrease in its conduction losses which is governed by its specific on-resistance. This on-resistance depends on the resistance of the channel and the n-drift region of the device.

Figure 4.34: Mobility close to the surface in the gate region (left), and reverse biased characteristics (right) in 6H-SiC accumulation- and inversion-mode lateral DMOSFET.

An estimate of the on-resistance contribution indicates that 90% of the on-resistance is due to the large channel resistance, owing to the low inversion layer mobility. The proposed structure is able to minimize this resistance and improve the mobility. A simulated accumulation layer mobility of 120 cm$^2$/Vs compared to the 60 cm$^2$/Vs for the inversion-layer was observed as shown in Fig. 4.34 (left).

A breakdown voltage of $1460\,\mathrm{V}$ with a leakage current comparable to that of standard inversion-mode LDMOSFET was achieved as shown in Fig. 4.34 (right). The off-state leakage current caused by the built-in potential of the p/n junction is ten orders of magnitude less than the on-state current for the same structure, but one order of magnitude larger than the inversion-mode structure. This can effectively be suppressed by calibrating parameters which enable a fully depleted accumulation-layer. High temperature causes an increase in the leakage current due to the increased intrinsic carrier concentration.

The proposed structure offers the possibility to serve as a shield to the influence of the high SiC bulk electric field on the gate oxide. The influence of the accumulation-layer thickness on the electric filed in Fig. 4.35 shows the new structure at accumulation-layer thickness of 0.3$\mu$m reduced the the electric filed by 0.3MV/cm. Thereby, the peak surface electric field at the maximum blocking voltage has been kept below 1.5 MV/cm which is equivalent to the oxide field of 3.75 MV/cm, and considerably lower than the practical limit of the electric field strength in the oxide.

Figure 4.35: Effect of the accumulation layer thickness on the electric field (left), and the electric field profile at the maximum blocking voltage (right) in 6H-SiC accumulation-mode lateral DMOSFET.

T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation