4.3 ETCH3D -- Topography Simulator

Etching is used in various steps during the fabrication of an integrated circuit (IC). It is e.g. used to transfer the pattern comprising the design of the integrated circuit (IC) layout from the resist layer as it is created by lithography onto the Wafer. Another example of an etch step is to remove layers of material (e.g. masks) from the Wafer. Several techniques to simulate etching and deposition processes were developed in the past.

Polygonal (string/segment-based) methods, represent the surface as a list of line segments in two dimensions and a list of triangles in three dimensions. The advantage of this representation is that the simulator internal data structures are already polygonal which allows for an easy coupling of the resulting topography to grid-based simulators. However, the major disadvantages are hard to detect non-physical loops and self intersections that might occur during the simulation. A three-dimensional implementation of this algorithm can be found in [67].
Monte-Carlo methods work on an atomistic level. They are focused on physical and chemical particle-particle interactions [68]. As with other Monte-Carlo-based simulations a drawback is the consumption of comparably large amounts of computing power.
In level-set methods the interface between two materials is determined by a bounded transition function that is defined on the grid. If the value of this function ranges from e.g. to , then the interface between the two materials is (implicitly) defined as the iso-area with a function value of 0. A very complete compilation of different applications of topography simulations based on the level set method is given in [69].
In cellular methods the geometry is represented by a number of orthogonal cells. A so-called structuring element is moved along the surface of the geometry and removes (or deposits) material. By varying size and shape of the structuring element different etching rates as well as isotropic, anisotropic and unidirectional etching and deposition can be modeled. As a major disadvantage the elaborate post-processing step to convert the cellular geometry description to a polygonal geometry description must be mentioned.

The etching simulator previously developed at the Institute for Microelectronics [70,71,72,73,74,75,76] is based on a cellular approach.

The etching simulation poses by far the strongest demands on the WAFER-STATE-SERVER library. It uses the I/O layer to read and to create a persistent Wafer. After the etching simulation is completed a complex post-processing step that extracts the geometry information from the etching front and merges it with the input Wafer is performed.

Subsections

2003-03-27


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