6.3.1.1 Dependence on the Gate-to-Channel Separation

In  Figure 6.41 g_{m max} is shown over a wider range of d_GC. Within the accuracy of the simulation g_{m max} is increased linearly with about 28 mS/mm for a reduction of d_GC by 1 nm. The simulations are performed under the assumption that the Schottky barrier height F_B is constant. One has to expect a deteriorated F_B if the distance between the gate and the delta doping gets below a certain value.
 

It is shown in  Figure 6.41 that the threshold voltage V_T is also very sensitive to d_GC. V_T is shifted by about 75 mV for a change of d_GC of only 1 nm, thus very tight process control is necessary to provide high uniformity over the wafer which is an important requirement for digital ICs [81, 82]. A high reproducibility even from one wafer to another is required for ICs with only a positive bias voltage were only enhancement mode HEMTs can be used.
 

• 6.3.1.2 Dependence on the Gate Length
• 6.3.2 RF Performance
• 6.3.2.1 Dependence on the Gate Length
• 6.3.2.2 Contributions to the Gate Capacitance
• 6.3.2.3 Dependence of f_T on d_GC
• 6.3.2.4 Dependence of f_T and f_max on L_R
• 6.3.2.5 Dependence on the Passivation Thickness
• 6.3.3 Optimization of Millimeter Wave HEMTs
• 6.4 Comparison between Low Noise, Power, and Millimeter Wave HEMTs
• 6.5 Influence of Backside Doping on the C_G(V_GS) Characteristics