5.1 Grid Requirements for Device Simulation

As an example, consider the long channel nMOSFET shown in Figure 5.1, operating in inversion mode. We assume no recombination and stationary conditions. No voltage is connected between source and drain, and therefore the device is current-free. To compensate the electric field in the channel arising from the applied gate voltage, a carrier displacement will occur in that area.

Figure 5.1: Structure of a two-dimensional MOS transistor.

The set of equations are the Poisson equation and the semiconductor equations

$$\operatorname{div}\;(\varepsilon \;\operatorname{grad}\phi)= \mathrm{q} \;(n-p-(N_A - N_D)),$$ (5.1)

$$\operatorname{div}{\mathrm{\bf J}}_n - \mathrm{q} \;\frac{\partial n}{\partial t}=\mathrm{q} \;R,$$ (5.2)

$$\operatorname{div}{\mathrm{\bf J}}_p + \mathrm{q} \;\frac{\partial p}{\partial t}=-\mathrm{q} \;R,$$ (5.3)

$${\mathrm{\bf J}}_n = -\mathrm{q} \;\mu_n \;n \;\operatorname{grad}\phi+ \mathrm{q} \;D_n \;\operatorname{grad}n,$$ (5.4)

$${\mathrm{\bf J}}_p = -\mathrm{q} \;\mu_p \;p \;\operatorname{grad}\phi- \mathrm{q} \;D_p \;\operatorname{grad}p.$$ (5.5)

In inversion mode, the holes under the gate are displaced and the following relation holds

$$n \gg N_A - N_D \gg p.$$ (5.6)

The holes become negligible and only the drift-diffusion current relation for the electrons has to be considered. Without recombination and in stationary mode the required equations simplify to ( $\mu_n V_\mathrm{th}= D_n$)

$$\operatorname{div}\;(\varepsilon \;\operatorname{grad}\phi) = \mathrm{q} \; n,$$ (5.7)

$$\operatorname{div}{\mathrm{\bf J}}_n = 0,$$ (5.8)

$${\mathrm{\bf J}}_n = -\mathrm{q} \;\mu_n \;n \;\operatorname{grad}\phi+ \mathrm{q} \;\mu_n \;V_\mathrm{th}\;\operatorname{grad}n.$$ (5.9)

It is obvious that carrier displacement occurs only along the y-axis, in the direction of the electric field and therefore only the y-component of equations (5.8) and (5.9) is crucial

$$J_{n,y} = \mathrm{q} \;\mu_{n} \;n \;E_y + \mathrm{q} \;\mu_n \;V_\mathrm{th}\;\frac{\partial n}{\partial y} = 0.$$ (5.10)

This equation system can be solved by differentiating equation (5.7) (only the y-component of the electric field is present). We assume constant permittivity and mobility, and obtain

$$\varepsilon \;\frac{\partial^{2} E_y}{\partial y^2} = - \mathrm{q} \;\frac{\partial n}{\partial y}.$$ (5.11)

Inserting (5.7) and (5.11) into (5.10) gives

$$- \varepsilon \;\frac{\partial E_y}{\partial y} \;E_y - V_\mathrm{th}\;\varepsilon \;\frac{\partial^2 E_y}{\partial y^2}=0$$ (5.12)

which is an ordinary differential equation in $E_y$ ( $E_y'=\frac{\partial}{\partial y} E_y$)

$$E_y'' + \frac{1}{V_\mathrm{th}} \;E_y \;E_y' = 0.$$ (5.13)

This equation shows an unphysical solution $E_y \propto \tanh (y+d)$, which leads from the additional differentiation (5.11), and the solution $E_y=A/(y+d)$, where both the electric field and the carrier concentration decay to zero. With the evaluation of $A$ the final solution is

$$E_y=2 \;V_\mathrm{th}\;\frac{1}{y+d}.$$ (5.14)

The parameter $d$ is affected by the thickness of the field-oxide, the applied voltage, and the dopant concentrations. By insertion into (5.7), the distribution of the charge carriers follows as

$$n=\frac{2 \;V_\mathrm{th}\;\varepsilon }{\mathrm{q}} \;\frac{1}{(y+d)^2}.$$ (5.15)

Here it can be seen that the electric field and even more, the carrier concentration changes rapidly along the y-axis, whereas along the x-axis the values remain unchanged. In Figure 5.2 the resulting carrier concentration of such a device is shown. Here the silicon segment has a constant donor background doping of $10^{15} \mathrm{cm^{-3}}$ and the highly doped areas under the source and drain contacts have a constant acceptor doping of $10^{20} \mathrm{cm^{-3}}$. The oxide thickness under the gate contact is 20  nm. By applying a drain-source voltage and without a gate-source voltage, one of the two source/silicon or drain/silicon pn-junctions are in reverse direction and the device is blocked. With a gate bias of 10  V and all other contacts grounded, the carrier concentrations raise at the gate regions. The device is in inversion and the carrier concentrations under the gate contact are higher than the concentrations in the source and drain regions. The pn-junctions are not reverse biased any longer.

With introducing a voltage between source and drain, a current will arise. As the free charge carriers are responsible for the current density, a relatively high current density change along the y-axis, combined with nearly constant current density along the x-axis will follow. In Figure 5.1, the current density, with a voltage of 1  V between source and drain, is shown. Along the channel, the current density is almost constant. This simple device with planar silicon surfaces has been simulated based on an ortho grid. The comparison of different grid approaches, with a dense grid with a grid spacing of 0.01  nm along the y-axis and a coarse grid with minimum grid distance of 20  nm under the gate, and the result of the analytical solution is shown in Figure 5.1. The analytical solution loses its validity since relation (5.6) is violated. Comparing the simulations, an underestimation of the current density under the gate contact of about $1:30$ can be detected, which may decide about an breakdown of the device in critical cases.

Figure 5.2: The carrier concentration of the two-dimensional device simulation with a gate-source and gate-substrate voltage of 10  V.

Figure 5.3: The current density of the two-dimensional device simulation at $V_{\textrm {DS}}=1 \textrm {V}.$

Figure 5.4: Comparison of the simulation approaches. The first two-dimensional simulation is performed on a dense grid with a grid spacing of 0.01 nm under the gate. The coarse grid has a spacing of 20 nm under the gate. These simulations are compared with the derived analytical solution, $n_0=3.38\times 10^{5} \textrm {cm}^{-1}, d=0.32 \textrm {nm}.$