3.1 Compact Modeling with Discrete Devices

Especially in the context of large scale integrated circuits, modeling of hysteresis with the standard devices provided by the well-known circuit simulator SPICE [Nag75] is very useful.

Figure 3.1: Parallelogram shaped hysteresis

The simplest model approximates the shape of the hysteresis in the form of a parallelogram, as sketched in Fig. 3.1. The circuit, as outlined in Fig. 3.2, consists of a history dependent voltage source $V_\mathrm{P}$ and two additional capacitors. These two capacitors are connected to the input voltage $V_\mathrm{IF}$. In order to model bulk parasitics, two diodes are added to the circuit in parallel and in series. The output quantity of this model is the charge which is stored at the nodes 1 and 2.

Figure 3.2: SPICE based compact model with parallelogram shaped hysteresis

It has to be mentioned that the shape of the hysteresis function resulting from this model, the parallelogram, only offers a poor fit to the physical properties, as it does not reproduce the shape very accurately.

In 1994 Dunn [Dun94] proposed an extension of this model which allows the simulation of transient behavior. This model simulates the relaxation currents with two exponential terms and two different time constants $\tau_1$ and $tau_2$ as follows:

$$I(t)=I_\mathrm{0}\cdot(e^{-t/\tau_1} - e^{-t/\tau_2}).$$ (3.1)

These properties can be added to the SPICE model by a modification of the history dependent voltage source $V_\mathrm{P}$. This modification is achieved by the introduction of additional RC circuits.

Different approaches were tried in the field of magnetic hysteresis by Brachtendorf et al. [BEL97], based on theoretical work of Jiles and Atherton [JA86]. These have an increased capacity to reproduce the actual shape of the hysteresis function.