List of Figures

• 1.1. Comparison of sizes of semiconductor manufacturing process nodes since the early 1970s.
• 1.2. Numbering of material regions in (a) leads to the Level Set description in (b).
• 1.3. The simulation of particle transport, which is divided into the reactor-scale and feature-scale regions.
• 2.1. Difference in uses of thermally grown versus deposited silicon dioxide in silicon technology.
• 2.2. (a) Structure of fused silica glass along with (b) a six-membered ring structure of SiO$_2$.
• 2.3. Moving interfaces and volume expansion after silicon oxidation.
• 2.4. Atomistic configurations of the Si-SiO$_2$ interface.
• 2.5. LOCOS processing steps
• 2.6. STI processing steps
• 2.7. Oxide thickness versus oxidation time for dry (O$_2$) oxidation of a (100) oriented silicon wafer under various temperatures.
• 2.8. Oxide thickness versus oxidation time for wet (H$_2$O) oxidation of a (100) oriented silicon wafer under various temperatures.
• 2.9. Oxide thickness versus process temperature for wet (H$_2$O) and dry (O$_2$) oxidation of a (100) oriented silicon wafer at 1000 $^\textrm {o}$C.
• 2.10. Effects of hydrostatic pressure on thermally grown oxide thickness for a (100) oriented silicon wafer in a) dry (O$_2$) and b) wet (H$_2$O) ambients.
• 2.11. Oxide thickness versus oxidation time for (100) and (111) oriented silicon by wet oxidation at various temperatures.
• 2.12. One-dimensional Deal-Grove model for the oxidation of silicon.
• 2.13. Comparison between the Deal Grove and Massoud models for the oxide thickness during the first hour of oxidation in a dry ambient on (100) oriented silicon.
• 2.14. Typical STM schematic for surface imaging.
• 2.15. Typical AFM schematic for surface imaging.
• 2.16. Generation of a water meniscus between the AFM tip and silicon substrate after a negative voltage is applied.
• 3.1. Modeling approach when a single LS interface is split into two interfaces, which move in opposite directions for a 500$\times$500 geometry moving at velocities 0.25 and -0.75 for the top and bottom surfaces, respectively.
• 3.2. Modeling approach when the initial LS geometry contains two interfaces which need to be moved in opposite directions, for a 500$\times$500 geometry at velocities 0.25 and -0.75 for the top and bottom surfaces, respectively.
• 3.3. Modeling approach when the initial LS geometry contains two interfaces, one a mask and one a surface to be grown. A 15$\times$15$\times$5 geometry is used.
• 3.4. Geometry of a mask and its LS labeling when the mask is used for a material growth or deposition process.
• 3.5. The initial and final geometry after surface evolution of $\Phi _{down}$ downward and $\Phi _{up}$ upward at rates of -0.25 and 0.75, respectively.
• 3.6. Simulation of the translation of a sphere under vector motion. The sphere has a radius of 50 grid points and is moving downward at a rate of 1 grid point per time unit for 250 time units.
• 3.7. Phase diagram of the Nitric acid (HNO$_3$/H$_2$O) system.
• 3.8. The dependence of immersion time and temperature on the growth of NAOS oxide submersed in a 61wt% HNO$_3$ solution.
• 3.9. Plots of the SiO$_2$ thickness with respect to the oxidation time at different temperatures when the vapor NAOS method is used. Dots are experimental results from [103] and lines are the results of the presented empirical model.
• 3.10. Oxidation driven by oxyions, which are generated due to the presence of the strong electric field, interacting with the silicon surface.
• 3.11. Modeling approach for a hemispherical AFM needle tip versus a rough AFM needle tip. (a) Dot charge used to model AFM with a hemispherical needle tip and (b) Ring of charges used to model AFM with a rough needle tip.
• 3.12. The width of the oxide lines on a silicon substrate as a function of the applied bias, from [109].
• 3.13. Height of the oxide as a function of the applied voltage, as presented in[192] and implemented in the presented simulator.
• 3.14. FWHM of the oxide as a function of the applied voltage. Measurements are from[192], while the simulations are from (3.44).
• 3.15. Height and width of the oxide nanodot as a function of the applied voltage and pulse time.
• 3.16. Effects of humidity on the nanodot height and width, as presented in [53].
• 3.17. Effects of time, voltage, humidity, and orientation on the nanowire height and width. Experimental (dots) and model (lines) values are shown.
• 3.18. Effects of wire orientation on the nanowire height and width, with $t$=0.1ms, $V_b$=7V, and $h$=55%. The vertical axis is scaled by 100 for better visualization. The top surface represents the oxide-ambient interface, while the lower surface represents the oxide-silicon interface.
• 3.19. Image representation of the MC method of ``imprinting'' a desired particle distribution onto the silicon surface in order to generate an oxide growth. The particles are accelerated using ray tracing techniques within the LS simulator environment.
• 3.20. Flow chart of the simulation process implementing the Monte Carlo method with ray tracing in a LS environment.
• 3.21. Nanodot generated using Gaussian particle distribution. The vertical dimension has been scaled by 20 for better visualization. (a) NCM nanodot generated using a Gaussian distribution of particles and (b) Diagonal cross-section of the nanodot from Figure 6.13a
• 3.22. (a) Comparison between the Gaussian distribution and the surface charge density and (b) comparison between the Lorentzian distribution and the surface charge density.
• 3.23. Cross-sectional nanodot height generated using a Lorentzian distribution.
• 3.24. The vertical dimension has been scaled by 20 for better visualization. (a) NCM nanodot generated using a Lorentzian distribution of particles and (b) Diagonal cross-section of the nanodot
  from Figure 3.24a.
• 3.25. Normalized effective nanodot cross section height and the normalized SCD function.
• 3.26. The effective diagonal cross-section height of a nanodot when using a rough AFM needle tip versus a hemispherical AFM needle tip.
• 4.1. Summary of chemical thin film deposition technologies.
• 4.2. General schematic of a spray pyrolysis deposition process.
• 4.3. Single jet and multi jet modes of electrostatic spray deposition.
• 4.4. Spray pyrolysis droplets modifying as they are transported from the atomizing nozzle to the substrate. Whether the temperature[216] or the initial droplet size[187] are varied, there are four potential paths which the droplet can take as it moves towards the substrate (A-D).
• 4.5. Air temperature above a heated plate for substrate temperatures 210$^o$C, 250$^o$C, 310$^o$C, and 400$^o$C during a pressurized spray process.
• 4.6. Technology scaling for FLASH memory.
• 4.7. Image of a typical BiCS structure with memory holes.
• 5.1. The droplet transport in the space above the substrate surface and the accelerations which are considered in the transport model. T$_{th}$ is the height of the thermal zone ($\sim$10mm for ESD, $\sim$5mm for PSD), and H is the distance between the substrate and atomizer.
• 5.2. The effects of varying the atomizing nozzle's outer radius on the strength of the electric field with and without the inclusion of the $K_V$ effects.
• . Magnitude of the normalized electric potential $\Phi\slash\Phi_0$ during ESD processing. The distance between needle and deposition plate as well as the radial distance from the center are normalized to the distance between the atomizer and the substrate. The inset is the normalized electric field distribution.
• 5.4. Droplet impact onto a heated surface, resulting in the spreading of a thin film in a disc-like shape.
• 5.5. Two-dimensional image of the hole which needs to be etched through layers of Si and SiO$_2$ in order to generate a BiCS structure.
• 5.6. Images showing the etched SiO$_2$ topography when using a fluorocarbon gas as the etchant, implemented using the described model.
• 5.7. Images showing the etched SiO$_2$ topography when using fluorocarbon gas as the etchant for various polymer sticking coefficients $s_p$.
• 5.8. The effects of SiO$_2$ tapered angles during silicon etching using a HBr/O$_2$ plasma.
• 6.1. Results of the oxidation of (100) oriented silicon in a dry ambient at 1atm pressure and 1000 $^{\textrm {o}}$C temperature for 100 minutes. The top surface (red) depicts the SiO$_2$-ambient interface, while the lower surface (blue) depicts the location of the $\textrm {Si-SiO}_{2}$ interface. The volume shown is the original location of the silicon substrate.
• 6.2. Results of the oxidation of (100) oriented silicon in a dry ambient at 1atm pressure and 1000 $^{\textrm {o}}$C temperature for 100 minutes with 10nm of native oxide present. The top surface (red) depicts the SiO$_2$-ambient interface, while the lower surface (blue) depicts the location of the Si-SiO$_2$ interface. The volumes shown are the original location of the silicon substrate and the native oxide.
• 6.3. Results of the oxidation of a trench etched into (100) oriented silicon with (110) oriented sidewalls. in a dry ambient at 1atm pressure and 1000 $^{\textrm {o}}$C temperature for 100 minutes. The top surface (red) depicts the SiO$_2$-ambient interface, while the lower surface (blue) depicts the location of the Si-SiO$_2$ interface. The volumes shown is the original location of the silicon trench.
• 6.4. Geometry of the bird's beak occurrence during LOCOS processing. $H_{bb}$ and $L_{bb}$ describe the maximum height and length of the nitride after oxidation, respectively.
• 6.5. Bird's beak length and height dependences on nitride and pad oxide thicknesses from[190]. The field oxide is simulated to grow at $1000^{\textrm {o}}$C for a thickness of approximately 600nm.
• 6.6. Thermal oxidation with the bird's beak effect. The field oxide is simulated to grow on (100) silicon at 1000 $^{\textrm {o}}$C in a wet environment for 2 hours, resulting in a field oxide thickness of approximately 600nm. The oxide thickness is 15nm and the nitride thickness is (a)-(b) 200nm and (c)-(d) 100nm.
• 6.7. Results of the oxidation of (100) oriented silicon during immersion in a 61wt% HNO$_3$ concentration at a temperature of 60 $^{\textrm {o}}$C. The top surface (red) depicts the SiO$_2$-ambient interface, while the lower surface (blue) depicts the location of the Si-SiO$_2$ interface. The volume shown is the original location of the silicon substrate.
• 6.8. Effects of pulse time on the AFM nanodot height and width. The vertical axis is scaled by 20 for better visualization.
• 6.9. Effects of ambient humidity on the AFM nanodot height and width. The vertical axis is scaled by 20 for better visualization.
• 6.10. Effects of bias voltage on the AFM nanodot height and width. The vertical axis is scaled by 20 for better visualization.
• 6.11. Nanowire topography simulated using a sequence of AFM nanodots (top) and the nanowire's cross-section (bottom).
• 6.12. Simulations of AFM-generated nanowires.
• 6.13. Simulations of AFM-generated nanodots for ROM applications. (a) Image of $\pi$ in binary code, written with oxide nanodots on a silicon surface from[59]. (b) Simulated image of $\pi$ in binary code, repeating the experiment from[59], with inset of a proportional Figure 6.13c. (c) Simulated image of $\pi$ in binary code. with improved aerial density.
• 6.14. SiNWT generated using AFM nanolithography and wet etching [85].
• 6.15. Topography simulation steps for the fabrication process for a silicon nanowire transistor. (a) Initial lithography to place oxide as a mask for source, drain, and gate contacts. (b) Nanowire generated using AFM to connect the source and drain contacts. (c) TMAH etching of silicon, with SiO$_2$ serving as a mask. (d) HF etching of SiO$_2$, leaving the desired pattern on the silicon surface.
• 6.16. Macroscopic spray pyrolysis simulation on a 50mm by 50mm geometry. Each spray cycle contains 100,000 droplets.
• 6.17. Microscopic spray pyrolysis simulation on a 250$\mu$m by 250$\mu$m geometry.
• 6.18. Schematic for the PSD spray pyrolysis process used at AIT, serving as a basis for the presented topography simulations.
• 6.19. Images showing the deposited SnO$_2$ film as a results of a PSD deposition step. The good step coverage confirms a chemical and not physical reaction takes place during deposition.
• 6.20. The initial and final topographies after applying Si and SiO$_2$ etching models for the fabrication of BiCS memory holes.