Over the last three decades our way of life was dramatically changed by the spread of new electronic appliances. Important achievements like personal computers, mobile phones, or the world wide web form a new digital world, a world driven by the progress in semiconductor device and process research and development.
By far the most widely used semiconductor device for logic integrated circuits is the metal-oxide-semiconductor field-effect transistor (MOSFET). It is implemented exclusively on Si substrates. The main reason for the impressive performance improvements over the last decades results from the down scaling of this device. Scaling does not just allow to integrate more transistors within one circuit. When making the devices smaller they also exhibit reduced switching times and reduced power consumption. As predicted by the International Technology Road-map for Semiconductors [SIA06] this trend is expected to continue in the coming decade and then coming to an end because of rising costs when scaling is pushed close to principal physical limits [Haensch06].
These limits are, on the one hand, related to the fabrication process
itself. It gets more and more challenging to achieve the needed resolution in
lithography for the next technology node. On the other hand, important device
properties do not benefit from scaling any more, or even get worse. A major
problem in this respect is the gate leakage current, which raises exponentially
for smaller gate oxide thickness. For the upcoming
45
nm] technology node this problem is solved by the introduction of
metal gates and hafnium-based high-
dielectrics [Intel07]. With
further downscaling also variability in the delay and power consumption is
becoming an urgent problem for designers [Bernstein06].
Another problem is the increase of the source-drain
series resistance caused by the need for ultra-shallow p-n junctions in the
source-drain regions [Skotnicki05].
These problems slow down the scaling process significantly and already brought alternative approaches to improve device performance into focus. These approaches include new device designs like multi-gate MOSFETs or ultra thin body (UTB) MOSFETs as well as the introduction of strain engineering.
In this work the use of strained Si to improve the carrier mobility is explored with technical computer aided design (TCAD) methods. Whereas conventional TCAD simulators are based on drift-diffusion models, here, a full-band Monte Carlo (FBMC) simulator is developed which delivers more accurate and refined electrical transport properties of strained Si, Ge, and SiGe alloys. In the past the use of full-band Monte Carlo methods was limited by their high demand for computation time, so that their main purpose in TCAD was to deliver accurate data for calibration of less fundamental methods such as drift-diffusion. However, it is shown, that due to the ever increasing availability of computational power and with the implementation of CPU-time efficient algorithms, FBMC can be used for simulation of MOSFET devices [Jungemann03]. In this work FBMC is applied to explore blocked impurity band (BIB) devices [Petroff86]. These devices are photo detectors for the far infrared band which operate at very low temperatures.
In Chapter 2 a short introduction to the theory of stress and strain in elastic bodies is given. Next the conduction band structure of Si as well as the valence band structure of Ge is analyzed in detail. The band structure data are obtained with the empirical pseudopotential method (EPM). To improve the performance of EPM calculations and of FBMC simulations it is important to take advantage of the symmetry properties of the Brillouin zone. Therefore, the symmetry properties under several strain conditions are investigated in detail.
In Chapter 3 an introduction to the semi-classical Monte Carlo method is given, with emphasis on the algorithms and models actually implemented in the full-band simulator. This also includes a description of the methods used for meshing the Brillouin zone, which have a critical impact on the simulator performance and accuracy.
The Monte Carlo simulator is adopted to explore BIB devices in Chapter
4. These photo detectors for the far infrared range are mainly used in space
based observation facilities. BIB detectors deliver high quantum efficiency in
a volume much smaller than in conventional photoconductors because of their
much higher primary doping. The primary dopants form an impurity band, in which
significant hopping conduction occurs. To block dark current introduced by
hopping carriers the device features an undoped region, referred as
the blocking layer.
Some of the standard scattering models for
Monte Carlo have to be extended to deliver valid results for temperatures below
K. Also an approach for a non-Markovian impact ionization model is
presented. At the end of that chapter simulation results for a BIB device
operating as a photon counter are presented.