List of Figures
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- XLISP code to define a linear regression (
) model
- Interaction between TCAD shell, Task Agent, and Task Module.
- Comparison of Analytically Extracted Profile (solid-symbols) with
Profile Extracted using 10 (dashed) and 15 (dotted) equally
spaced knots for a MOS Capacitor with 70
oxide and 4000
area.
- Inverse Modeling (solid) and Analytical (dashed) extracted
profiles for a MOS Capacitor with 70 oxide and 4000 area.
- Residuals Sum of Squares (SSQ) as a function of number of knots
for the new placement algorithm (solid) and equally spaced knots (dashed).
- Simulated (solid) and experimental (symbols) deep depletion
C-V of a MOS Capacitor with 70 oxide and
area.
- N-channel source/drain 1D doping profiles: SIMS donor profile (dashed
line) and net doping extracted by inverse modeling from diode capacitance
with area of
.
- Simulated and experimental (symbols) reverse junction capacitance
of a area diode.
- Deep depletion channel (solid) and source/drain net profiles.
- Starting profile.
- Extracted profile.
- Comparison of experimental (symbols), simulation with starting
profile (dashed), and simulation with extracted profile (solid) gate to
source/drain capacitances
vs. 
at varying 
.
- Comparison of experimental (symbols), simulation with starting
profile (dashed), and simulation with extracted profile (solid)
inner sidewall source/drain diode capacitances
vs. 
at varying .
- A schematic diagram of half an N-channel MOSFET with an
n- implant angle.
- Extracted one-sided net doping at the SiO
/Si
interface (device A - solid line, device B - dashed line,
device C - dotted line).
-
Comparison of original (dashed), initial guess (dotted),
and extracted (solid) net doping at the SiO/Si interface for the
simulation experiment.
- Comparison of original (dashed), initial guess (dotted),
and extracted (solid) net doping at
depth into silicon for
the simulation experiment.
-
Extracted N-channel net doping along the
SiO/Si interface and the corresponding 95% confidence region.
- N-channel net doping at the
SiO/Si interface extracted with (solid line) and without (dashed line)
Gaussian charges to model RSCE.
- Comparison of CV characteristics of profiles A (solid)
and B (dashed).
- Comparison of Profile A (symbols) and the extracted profiles using
the analytical approach (dashed) and the inverse modeling
method (solid).
-
Comparison of Profile B (symbols) and the extracted profiles using
the analytical approach (dashed) and the inverse modeling
method (solid).
-
P-Channel extracted profile
-
Comparison of measured (symbols) and simulated (lines)
I-V characteristics in the linear region (
mV)
for three gate lengths (
= 0.45, 0.9 and 1.84 
m).
- Comparison of measured (symbols) and simulated (lines)
I-V results in the linear and saturation regions for devices with
.
- Comparison of measured (symbols)
(lower 3 curves)
and 
(upper 3 curves) capacitances with simulated results
(lines) as a function of 
and 
for device with
m.
- Comparison of measured (symbols) (lower 3 curves)
and (upper 3 curves) capacitances with simulated results
(lines) as a function of and for device with
m.
-
Comparison of measured (symbols) and simulated (lines)
values,
at = 3, 3.5, and 4 Volts, and gate length of 
-
Comparison of measured (symbols) and simulated with (solid line) and without
(dashed line) calibration of peak values,
as a function of gate lengths.
- Comparison of
SIMS data (symbols) with single Pearson
for amorphized region (dashed line) and channeled region (dotted line)
and dual Pearson model (solid line).
-
Simulated
and 
distributions for a 
m CMOS
technology.
-
Simulated and distributions for a m CMOS
technology.
-
Comparison of MINIMOS (symbols) and PCIM model (solid line) gate capacitance
calculated values for a device with length of 20m and width
of
m.
-
Comparison of MINIMOS (symbol) and PCIM model (solid lines) overlap capacitance
capacitance values for a device with length of m for varying
and width of 
.
-
Linear region characteristics at zero for devices of width
of with length of
, 
, and 
.
-
ID-VD characteristics at varying and for devices with
length of
, width of .
Martin Stiftinger
Tue Aug 1 19:07:20 MET DST 1995