The accurate determination of the effective electrical channel length
(
) of MOSFETs is of crucial importance for device and
circuit characterization.
As a dominant MOSFET device parameter, variation
effect on circuit performance and functionality has to be accounted for
during circuit design. With the magnitude of intra-die polysilicon length
variation becoming a significant fraction of inter-die and inter-wafer
variation, these variation can no longer be neglected as it was commonly
done in the past (e.g. [111]).
Indeed, the transistors in a circuit could have different value.
For large die size, sub-half micron ULSI microprocessor chips, characterizing
and understanding variation within the die is key to improving
simulation predictability as well as enhancing parameteric circuit
performance and process control. Furthermore, adjusting the circuit design
methodology to deal with this issue is a major challenge facing circuit
designers. A first step in this direction involves the accurate
characterization of these variations.
Classical 
extraction techniques [104][103][19]
cannot be used for the characterization of intra-die variation in submicron
technology. These methods require the use of two or more different length
devices, and are based on the following relationship between
and the polysilicon gate length 
:
where it is assumed that is constant for all devices and
that is equal to the drawn gate length.
For sub-half micron CMOS technology, these assumptions are violated.
Whereas Scanning or Transmission Electron Microscopy (SEM or TEM)
can be used to accurately determine , the destructive
nature of these techniques, and the need for multiple devices
limit their applicability for intradie measurements.
In [42] a simple and accurate gate length extraction method
valid down to device lengths of 
is described. It is based on the
fact that the gate-to-source/drain capacitance (
) in the inversion
region depends only on oxide thickness, geometrical device structure, device
gate width and length, and polysilicon doping. The oxide thickness can
accurately be determined using one accumulation capacitance measurement
on a long channel device [87]. This value is not expected to change
significantly for other device on the same die. The effects of variation in
the device structure can also be neglected [42]. Thus
the inversion capacitance of devices with large known width is mainly a
function of the polysilicon gate length and the average polysilicon
doping 
. These values can thus be extracted by matching experimental
and MINIMOS simulated values with the device biased in the
inversion region using nonlinear least-squares optimization.
The MINIMOS simulation takes into account quantum mechanical and
polysilicon depletion effects [87][33]. The
method is non-destructive and its accuracy is immune to process variation
which makes it applicable to intradie characterization. It is noted that the
method is not sensitive to the characteristics doping profile provided the
device is biased in the inversion regime. However, with an accurate
doping profile and value, and can be
extracted using data from a single device as opposed to the multiple
devices required for the other approaches.
In the following, an extension to the extraction technique
that bypasses the use of nonlinear least squares optimization is described.
With this modification, the method becomes computationally efficient
and could therefore be incorporated as part of routine measurement
procedures.