References

1

J. Lilienfiled, ``U.S. patents 1,745,175 (filed 1926, issued 1930), 1,877,140 (filed 1928, issued 1932), and 1,900,018 (filed 1928, issued 1933).''

2

W. Shockley, ``The Path to the Conception of the Junction Transistor,'' IEEE Trans. Electron Devices, vol. ED-23, no. 7, pp. 597-620, 1976.

3

D. Kahng and M. Atalla, ``U.S. patents, 3206670 & 3102230 (1960).''

4

P. Bondyopadhyay, ``Moore's Law Governs the Silicon Revolution,'' Proc. IEEE, vol. 86, no. 1, pp. 78-81, 1998.

5

G. Moore, ``Cramming more Components onto Integrated Circuits,'' Electronics, vol. 38, no. 8, pp. 114-117, 1965.

6

G. Moore, ``Lithography and the Future of Moore's Law,'' in Optical/Laser Microlithography VIII, pp. 2-17, 1995.

7

International SEMATECH, ``Intl. Technology Roadmap for Semiconductors (ITRS),'' 2001.
http://public.itrs.net.

8

R. Kircher and W. Bergner, Three-Dimensional Simulation of Semiconductor Devices.
Birkhäuser, 1991.

9

O. Heinreichsberger, S. Selberherr, and M. Stiftinger, ``Three-Dimensional MOS Device Simulation on a Connection Machine,'' in Proc. SIAM Conf. on Parallel Processing for Scientific Computing, pp. 388-393, 1992.

10

K. Kroell and G. Ackermann, ``Threshold Voltage of Narrow Channel Field Effect Transistors,'' Solid-State Electron., vol. 19, no. 1, pp. 77-81, 1976.

11

J. Mandelman and J. Alsmeier, ``Anomalous Narrow Channel Effect in Trench-Isolated Buried-Channel P-MOSFET's,'' IEEE Electron Device Letters, vol. 15, no. 12, pp. 496-498, 1994.

12

N. Shigyo, M. Konaka, and R. Dang, ``Three-Dimensional Simulation of Inverse Narrow-Channel Effect,'' Electron. Lett., vol. 18, no. 6, pp. 274-275, 1982.

13

M. Thurner, Dreidimensionale Modellierung von MOS Transistoren.
Dissertation, Technische Universität Wien, 1988.

14

M. Thurner, P. Lindorfer, and S. Selberherr, ``Numerical Treatment of Nonrectangular Field-Oxide for 3-D MOSFET Simulation,'' IEEE Trans. Computer-Aided Design, vol. 9, no. 11, pp. 1189-1197, 1990.

15

M. Thurner and S. Selberherr, ``Comparison of Long- and Short-Channel MOSFETs carried out by 3D-MINIMOS,'' in Proc. European Solid-State Device Research Conf., pp. 409-412, 1987.

16

M. Thurner and S. Selberherr, ``3D MOSFET Device Effects due to Field Oxide,'' in Proc. European Solid-State Device Research Conf., pp. 245-248, 1988.

17

M. Thurner and S. Selberherr, ``Three-Dimensional Effects Due to the Field Oxide in MOS Devices Analyzed with MINIMOS 5,'' IEEE Trans. Computer-Aided Design, vol. CAD-9, no. 8, pp. 856-867, 1990.

18

H. Gummel, ``A Self-Consistent Iterative Scheme for One-Dimensional Steady State Transistor Calculations,'' IEEE Trans. Electron Devices, vol. ED-11, no. 10, pp. 455-465, 1964.

19

S. Selberherr, Analysis and Simulation of Semiconductor Devices.
Wien, New York: Springer, 1984.

20

W. VanRoosbroeck, ``Theory of Flow of Electrons and Holes in Germanium and Other Semiconductors,'' Bell Syst. Techn. J., vol. 29, pp. 560-607, 1950.

21

A. DeMari, ``An Accurate Numerical Steady-State One-Dimensional Solution of the P-N Junction,'' Solid-State Electron., vol. 11, no. 1, pp. 33-58, 1968.

22

A. DeMari, ``An Accurate Numerical One-Dimensional Solution of the P-N Junction under Arbitrary Transient Conditions,'' Solid-State Electron., vol. 11, no. 10, pp. 1021-2053, 1968.

23

H. Loeb, R. Andrew, and W. Love, ``Application of 2-Dimensional Solutions of the Shockley-Poisson Equation to Inversion-Layer M.O.S.T. Devices,'' Electron. Lett., vol. 4, pp. 352-354, 1968.

24

J. Schroeder and R. Muller, ``IGFET Analysis Through Numerical Solution of Poisson's Equation,'' IEEE Trans. Electron Devices, vol. ED-15, no. 12, pp. 954-961, 1968.

25

E. Buturla, P. Cottrell, B. Grossman, K. Salsburg, M. Lawlor, and C. McMullen, ``Three-Dimensional Finite Element Simulation of Semiconductor Devices,'' in Proc. IEEE Intl. Solid-State Circuits Conference, pp. 76-77, 1980.

26

E. Buturla, P. Cottrell, B. Grossman, and K. Salsburg, ``Finite-Element Analysis of Semiconductor Devices: The FIELDAY Program,'' IBM J. Res. & Dev., vol. 25, no. 4, pp. 218-231, 1981.

27

E. Buturla, J. Johnson, S. Furkay, and P. Cottrell, ``A New 3D Device Simulation Formulation,'' in Proc. Numerical Analysis of Semiconductor Devices and Integrated Circuits, pp. 291-295, 1989.

28

R. Knepper, J. Johnson, S. Furkay, J. Slinkman, X. Tian, E. Buturla, R. Young, G. Fiorenza, R. Logan, Y. Huang, R. O'Brien, C. Murthy, P. Murley, J. Peng, H. Tang, G. Srinivasan, M. Pelella, D. Sunderland, J. Mandelman, D. Lieber, E. Farrell, and M. Kurasic, ``Technology CAD at IBM,'' in Technology CAD Systems, pp. 25-62, Springer, 1993.

29

IBM Visualization Data Explorer Symposium, IEEE Visualization '96, ACM/SIGGRAPH, 1996.

30

F. Gaensslen, ``Geometry Effects of Small MOSFET Devices,'' in Proc. Intl. Electron Devices Meeting, pp. 512-515, 1976.

31

W. Lee, S. Laux, M. Fischetti, G. Baccarani, A. Gnudi, J. Stork, J. Mandelman, E. Crabbé, M. Wordeman, and F. Odeh, ``Numerical Modeling of Advanced Semiconductor Devices,'' IBM J. Res. & Dev., vol. 36, no. 2, pp. 208-232, 1992.

32

S. Chamberlain and A. Husain, ``Three-Dimensional Simulation of VLSI MOSFET's,'' in Proc. Intl. Electron Devices Meeting, pp. 592-595, 1981.

33

A. Husain and S. Chamberlain, ``Three-Dimensional Simulation of VLSI MOSFET's: The Three-Dimensional Simulation Program WATMOS,'' IEEE J. Solid-State Circuits, vol. SC-17, no. 2, pp. 261-268, 1982.

34

N. Shigyo and R. Dang, ``Analysis of an Anomalous Subthreshold Current in a Fully Recessed Oxide MOSFET Using a Three-Dimensional Device Simulator,'' IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 441-445, 1985.

35

N. Shigyo, S. Fukuda, T. Wada, K. Hieda, T. Hamamoto, H. Watanabe, K. Sunouchi, and H. Tango, ``Three-Dimensional Analysis of Subthreshold Swing and Transconductance for Fully Recessed Oxide (Trench) Isolated 1/4-$\mu$m-Width MOSFET's,'' IEEE Trans. Electron Devices, vol. ED-35, no. 7, pp. 945-951, 1988.

36

T. Toyabe, H. Masuda, Y. Aoki, H. Shukuri, and T. Hagiwara, ``Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms,'' IEEE Trans. Electron Devices, vol. 32, no. 10, pp. 2038-2044, 1985.

37

M. Thurner and S. Selberherr, ``The Extension of MINIMOS to a Three-Dimensional Simulation Program,'' in Proc. Numerical Analysis of Semiconductor Devices and Integrated Circuits, pp. 327-332, 1987.

38

S. Odanaka and T. Nogi, ``Massively Parallel Computation Using a Splitting-Up Operator Method for Three-Dimensional Device Simulation,'' IEEE Trans. Computer-Aided Design, vol. 14, no. 7, pp. 824-832, 1995.

39

S. Odanaka, M. Wakabayashi, H. Umimoto, A. Hiroki, K. Ohe, K. Moriyama, H. Iwasaki, and H. Esaki, ``SMART: Three-Dimensional Process/Device Simulator Integrated on a Super-Computer,'' in Proc. Intl. Symp. Circuits and Systems, pp. 534-537, 1987.

40

T. Linton and P. Blakey, ``A Fast, General Three-Dimensional Device Simulator and Its Application in a Submicron EPROM Design Study,'' IEEE Trans. Computer-Aided Design, vol. 8, no. 5, pp. 508-515, 1989.

41

J. Chern, J. Maeda, L. Arledge, and P. Yang, ``SIERRA: A 3-D Device Simulator for Reliability Modeling,'' IEEE Trans. Computer-Aided Design, vol. 8, no. 5, pp. 516-527, 1989.

42

P. Ciampolini, A. Forghieri, A. Pierantoni, A. Gnudi, M. Rudan, and G. Baccarani, ``Adaptive Mesh Generation Preserving the Quality of the Initial Grid,'' IEEE Trans. Computer-Aided Design, vol. 8, no. 5, pp. 490-500, 1989.

43

P. Ciampolini, A. Pierantoni, and G. Baccarani, ``Efficient 3-D Simulation of Complex Structures,'' IEEE Trans. Computer-Aided Design, vol. 10, no. 9, pp. 1141-1149, 1991.

44

P. Ciampolini, A. Pierantoni, M. Melanotte, C. Cecchetti, C. Lombardi, and G. Baccarani, ``Realistic Device Simulation in Three Dimensions,'' in Proc. Intl. Electron Devices Meeting, pp. 131-134, 1989.

45

G. Heiser, Design and Implementation of a Three-Dimensional, General Purpose Semiconductor Device Simulator.
Hartung-Gorre Verlag, 1991.

46

G. Heiser, C. Pommerell, J. Weis, and W. Fichtner, ``Three-Dimensional Numerical Semiconductor Device Simulation: Algorithms, Architectures, Results,'' IEEE Trans. Computer-Aided Design, vol. 10, no. 10, pp. 1218-1230, 1991.

47

M. Noell, S. Poon, M. Orlowski, and G. Heiser, ``Study of 3-D Effects in BOX Isolation Technologies,'' in Proc. Simulation of Semiconductor Devices and Processes, pp. 331-340, 1991.

48

P. Conti, N. Hitschfeld, and W. Fichtner, ``$\Omega$ - An Octree-Based Mixed Element Grid Allocator for Adaptive 3D Device Simulation,'' in Proc. Intl. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, pp. 25-26, 1990.

49

P. Conti, Grid Generation for Three-Dimensional Semiconductor Device Simulation.
Hartung-Gorre, 1991.

50

R. Bellens, P. Heremans, G. Groeseneken, and H. Maes, ``Analysis of Mechanisms for the Enhanced Degradation During AC Hot Carrier Stress of MOSFET's,'' in Proc. Intl. Electron Devices Meeting, pp. 212-215, 1988.

51

K. Wu, G. Chin, and R. Dutton, ``A STRIDE Towards Practical 3-D Device Simulation - Numerical and Visualization Considerations,'' IEEE Trans. Computer-Aided Design, vol. 10, no. 9, pp. 1132-1140, 1991.

52

A. Adamsone and B. Polsky, ``3D Numerical Simulation of Transient Processes in Semiconductor Devices,'' COMPEL, vol. 10, no. 3, pp. 129-139, 1991.

53

M. Liang and M. Law, ``An Object-Oriented Approach to Device Simulation-FLOODS,'' IEEE Trans. Computer-Aided Design, vol. 13, no. 10, pp. 1235-1240, 1994.

54

M. Law, FLOODS/FLOOPS Manual.
Univeristy of Florida, Department of Electrical Enginieering, 2000.
http://www.tec.ufl.edu.

55

H. Sheng, R. Guerrieri, and A. Sangiovanni-Vincentelli, ``Massively Parallel Computation for Three-Dimensional Monte-Carlo Semiconductor Device Simulation,'' in Proc. Simulation of Semiconductor Devices and Processes, pp. 285-290, 1991.

56

T. Smy, D. Walkey, and S. Dew, ``A 3-D Thermal Simulation Tool for Integrated Devices--Atar,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 105-115, 2001.

57

A. Asenov, ``Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 $\mu$m MOSFET's: A 3-D ``Atomistic'' Simulation Study,'' IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, 1998.

58

A. Asenov, A. Brown, J. Davies, and S. Saini, ``Hierarchical Approach to ``Atomistic'' 3-D MOSFET Simulation,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 11, pp. 1558-1565, 1999.

59

A. Asenov and S. Saini, ``Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100nm MOSFET's with Ultrathin Gate Oxide,'' IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 805-812, 2000.

60

S. Odanaka, K. Zaiki, and T. Nogi, ``Three-Dimensional Device Simulation on a Super Parallel Computer: ADENA,'' in Proc. Process/Device Modeling Workshop, pp. 122-125, 1990.

61

K. Traar, W. Mader, O. Heinreichsberger, S. Selberherr, and M. Stiftinger, ``High Performance Preconditioning on Supercomputers for the 3D Device Simulator MINIMOS,'' in Proc. Supercomputing '90, pp. 224-231, 1990.

62

S. Selberherr, M. Stiftinger, O. Heinreichsberger, and K. Traar, ``On the Numerical Solution of the Three-Dimensional Semiconductor Device Equations on Vector-Concurrent Computers,'' Comp. Phys. Comm., vol. 67, pp. 145-156, 1991.

63

R. Guerrieri, A. Sangiovanni-Vincentelli, E. Tomacruz, T. Toyabe, and D. Webber, ``Massively Parallel Algorithms for Three Dimensional Device Simulation,'' in Proc. Intl. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, pp. 35-36, 1990.

64

C. Fischer, P. Habaš, O. Heinreichsberger, H. Kosina, P. Lindorfer, P. Pichler, H. Pötzl, C. Sala, A. Schütz, S. Selberherr, M. Stiftinger, and M. Thurner, MINIMOS 6 User's Guide.
Institut für Mikroelektronik, Technische Universität Wien, 1994.
http://www.iue.tuwien.ac.at/software.

65

ISE, Technology CAD Overview.
ISE.
http://www.ise.com.

66

B. Witzigmann, A. Witzig, and W. Fichtner, ``A Full 3-Dimensional Quantum Well Laser Simulation,'' in Intl. Workshop on Computational Electronics, pp. 13-14, 2000.

67

F. Udrea, T. Trajkovic, J. Thomson, L. Coulbeck, P. Waind, G. Amaratunga, and P. Taylor, ``Ultra-high voltage device termination using the 3D RESURF (super-junction) concept - experimental demonstration at $6.5\,{\mathrm{kV}}$,'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 129 -132, 2001.

68

Y. Kawaguchi, T. Sano, and A. Nakagawa, ``20V and 8V Lateral Trench Gate Power MOSFETs with Record-Low On-Resistance,'' in Proc. Intl. Electron Devices Meeting, pp. 197-200, 1999.

69

A. Nakagawa and Y. Kawaguchi, ``Improved 20V Lateral Trench Gate Power MOSFETs with Very Low On-Resistance of $7.8\,{\mathrm{m}}\Omega\,{\mathrm{mm}}^2$,'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 47-50, 2000.

70

P. Roche, J. Palau, K. Belhaddad, G. Bruguier, R. Ecoffet, and J. Gasiot, ``SEU Response of an Entire SRAM Cell Simulated as One Contiguous Three-Dimensional Device Domain,'' IEEE Transactions on Nuclear Science, vol. 45, no. 6, pp. 2534-2543, 1998.

71

Avant!, Technology CAD Information.
Avant!
http://www.avanticorp.com.

72

S. International, ATLAS 5.2.0.R Release Note.
SILVACO International.
http://www.silvaco.com.

73

C. Fischer, Bauelementsimulation in einer computergestützten Entwurfsumgebung.
Dissertation, Technische Universität Wien, 1994.
http://www.iue.tuwien.ac.at/phd/fischer.

74

T. Simlinger, Simulation von Heterostruktur-Feldeffekttransistoren.
Dissertation, Technische Universität Wien, 1996.
http://www.iue.tuwien.ac.at/phd/simlinger.

75

S. Duvall, ``An Interchange Format for Process and Device Simulation,'' IEEE Trans. Computer-Aided Design, vol. 7, no. 7, pp. 741-754, 1988.

76

T. A. Vaughn and I. D. T. of Washington, CATIA Base Series - Set of 3 Manuals (CATIA Basics, Solids & Draw).
Design Technology of Washington, Inc., 1999.

77

C.-I. Division, Geant.
Cern.
http://wwwinfo.cern.ch/asd/geant.

78

SourceForge.net, GTS - GNU Triangulated Surface Library.
http://gts.sourceforge.net.

79

C. Wittine, ``Generation of Two-Dimensional Device Structures from One-Dimensional Topography, Profile and Layout Data,'' Diplomarbeit, Technische Universität Wien, 1998.

80

P. Conti and W. Fichtner, ``Automatic Grid Generation for 3d Device Simulation,'' in Proc. Simulation of Semiconductor Devices and Processes, pp. 497-505, 1988.

81

P. Conti, N. Hitschfeld, and W. Fichtner, ``$\Omega$ - An Octree-Based Mixed Element Grid Allocator for the Simulation of Complex 3-D Device Structures,'' IEEE Trans. Computer-Aided Design, vol. 10, no. 10, pp. 1231-1241, 1991.

82

N. Hitschfeld, P. Conti, and W. Fichtner, ``Mixed Element Trees: A Generalization of Modified Octrees for the Generation of Meshes for the Simulation of Complex 3-D Semiconductor Device Structures,'' IEEE Trans. Computer-Aided Design, vol. 12, no. 11, pp. 1714-1725, 1993.

83

P. Fleischmann, Mesh Generation for Technology CAD in Three Dimensions.
Dissertation, Technische Universität Wien, 1999.
http://www.iue.tuwien.ac.at/phd/fleischmann.

84

J. Cervenka, ``CGG: Ein Gittergenerator für die Bauelementesimulation,'' Diplomarbeit, Technische Universität Wien, 1999.

85

Y. Saad, ``SPARSKIT: A Basic Tool Kit for Sparse Matrix Computations,'' tech. rep., RIACS, NASA Ames Research Center, Moffett Field, CA 94035, 1990.

86

E. Cuthill and J. McKee, ``Reducing the Bandwidth of Sparse Symmetric Matrices,'' in Proc. ACM/CSC-ER Conf., pp. 157-172, 1969.

87

M. Hestenes and E. Stiefel, ``Methods of Conjugate Gradients for Solving Linear Systems,'' J. Res. Nat. Bur. Stand., vol. 49, no. 6, pp. 409-436, 1952.

88

H. Kosina, Computer-Aided Engineering: Technology and Devices.
Institut für Mikroelektronik, Technische Universität Wien, 2001.

89

R. Bank, D. Rose, and W. Fichtner, ``Numerical Methods for Semiconductor Device Simulation,'' IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1031-1041, 1983.

90

O. Heinreichsberger, Transiente Simulation von Silizium-MOSFETs.
Dissertation, Technische Universität Wien, 1992.
http://www.iue.tuwien.ac.at/phd/heinreichsberger.

91

H. van der Vorst, ``BI-CGSTAB: A Fast and Smoothly Converging Variant of BI-CG for the Solution of Nonsymmetric Linear Systems,'' SIAM J. Sci. Stat. Comput., vol. 13, no. 2, pp. 631-644, 1992.

92

AMTEC, TECPLOT 9.0.
http://www.amtec.com/.

93

IBM, Open Visualization Data Explorer.
http://www.research.ibm.com/dx/, http://www.opendx.org/.

94

W. Schroeder, K. Martin, and B. Lorensen, The Visualization Toolkit: An Object-Oriented Approach to 3D Graphics.
Prentice-Hall, 1996.

95

F. Preparata and M. Shamos, Computational Geometry.
New York: Springer, 1985.

96

D. Watson, ``Computing the $n$-Dimensional Delaunay Tessellation with Application to Voronoi Polytypes,'' The Computer Journal, vol. 24, no. 2, pp. 167-172, 1981.

97

T. Chen, D. Yergeau, and R. Dutton, ``Efficient 3D Mesh Adaptation in Diffusion Simulation,'' in Proc. Simulation of Semiconductor Processes and Devices, pp. 171-172, 1996.

98

G. Garretón, L. Villablanca, N. Strecker, and W. Fichtner, ``A New Approach for 2-D Mesh Generation for Complex Device Structures,'' in Proc. Intl. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, pp. 159-162, 1994.

99

J. Krause, L. Villablanca, N. Strecker, and W. Fichtner, ``Robust Anisotropic 3D Grid Generation Using a Normal Offsetting Approach,'' in Proc. Intl. Conf. on Numerical Grid Generation in Computational Field Simulations, pp. 1-7, 2000.

100

P. Fleischmann, E. Leitner, and S. Selberherr, ``Optimized Geometry Preprocessing for Three-Dimensional Semiconductor Process Simulation,'' in Proc. Intl. Conf. on Applied Modelling and Simulation, pp. 317-321, 1998.

101

P. Fleischmann, W. Pyka, and S. Selberherr, ``Mesh Generation for Application in Technology CAD,'' IEICE Trans.Electron., vol. E82-C, no. 6, pp. 937-947, 1999.

102

P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr, ``Grid Generation for Three-Dimensional Process and Device Simulation,'' in Proc. Simulation of Semiconductor Processes and Devices, pp. 161-166, 1996.

103

P. Fleischmann and S. Selberherr, ``A New Approach to Fully Unstructured Three-dimensional Delaunay Mesh Generation with Improved Element Quality,'' in Proc. Simulation of Semiconductor Processes and Devices, pp. 129-130, 1996.

104

D. Scharfetter and H. Gummel, ``Large-Signal Analysis of a Silicon Read Diode Oscillator,'' IEEE Trans. Electron Devices, vol. ED-16, no. 1, pp. 64-77, 1969.

105

T. Grasser, H. Kosina, M. Gritsch, and S. Selberherr, ``Using Six Moments of Boltzmann's Transport Equation for Device Simulation,'' J. Appl. Phys., vol. 90, no. 5, pp. 2389-2396, 2001.

106

W.-S. Choi, J.-G. Ahn, Y.-J. Park, H.-S. Min, and C.-G. Hwang, ``A Time Dependent Hydrodynamic Device Simulator SNU-2D With New Discretization Scheme and Algorithm,'' IEEE Trans. Computer-Aided Design, vol. 13, no. 7, pp. 899-908, 1994.

107

F. Fasching, The Viennese Integrated System for Technology CAD Applications-Data Level Design and Implementation.
Dissertation, Technische Universität Wien, 1994.
http://www.iue.tuwien.ac.at/phd/fasching.

108

T. Binder and S. Selberherr, ``Object-Oriented Wafer-State Services,'' in Proc. European Simulation Multiconf., pp. 360-364, 2000.

109

T. Binder and S. Selberherr, ``Object-Oriented Design Patterns for Process Flow Simulations,'' in Proc. Software Engineering and Applications, pp. 159-166, 2000.

110

C. Hollauer, ``Implementierung einer HDF5-Datenschnittstelle für den Wafer-State-Server,'' Diplomarbeit, Technische Universität Wien, 2002.

111

ISE, ISE TCAD Manuals Vol. 6, Release 4.
ISE Integrated Systems Engineering, 1997.

112

J. C. W.M., M. Pinto, and R. Smith, ``Adaptive Grid Generation for VSLI Device Simulation,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 10, pp. 1259-1275, 1991.

113

B. Rao, Object-Oriented Databases.
New York: McGraw-Hill, 1994.

114

J. Ullman, Database Systems.
Computer Science Press, 1982.

115

I$\mu$E, MINIMOS-NT 2.0 User's Guide.
Institut für Mikroelektronik, Technische Universität Wien, 2002.

116

R. Strasser, C. Pichler, and S. Selberherr, ``VISTA - A Framework for Technology CAD Purposes,'' in Proc. European Simulation Symposium, pp. 450-454, 1997.

117

R. Sedgewick, Algorithms in C.
Addison-Wesley, 1990.

118

D. Knuth, The Art of Computer Programming: Fundamental Algorithms, vol. 1.
Reading, Massachusetts: Addison-Wesley, 3rd ed., 1997.

119

B. Stroustrup, C++ Programming Language.
Addison-Wesley, 1997.

120

S.Wagner, ``The Minimos-NT Linear Equation Solving Module,'' Diplomarbeit, Technische Universität Wien, 2001.

121

R. Mlekus and S. Selberherr, ``Object-Oriented Algorithm and Model Management,'' in Proc. Intl. Conf. on Applied Modelling and Simulation, pp. 437-441, 1998.

122

R. Mlekus, Object-Oriented Algorithm and Model Management in TCAD Applications.
Dissertation, Technische Universität Wien, 1999.
http://www.iue.tuwien.ac.at/phd/mlekus.

123

C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, ``A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices,'' IEEE Trans. Computer-Aided Design, vol. 7, no. 11, pp. 1164-1171, 1988.

124

G. Masetti, M. Severi, and S. Solmi, ``Modeling of Carrier Mobility Against Carrier Concentration in Arsenic-, Phosphorus- and Boron-Doped Silicon,'' IEEE Trans. Electron Devices, vol. ED-30, no. 7, pp. 764-769, 1983.

125

W. Hänsch, M. Orlowski, and W. Weber, ``The Hot-Electron Problem in Submicron MOSFET,'' in Proc. European Solid-State Device Research Conf., pp. 597-606, 1988.

126

T. Grasser, Mixed-Mode Device Simulation.
Dissertation, Technische Universität Wien, 1999.
http://www.iue.tuwien.ac.at/phd/grasser.

127

W. Engl and H. Dirks, ``Numerical Device Simulation Guided by Physical Approaches,'' in Proc. Numerical Analysis of Semiconductor Devices and Integrated Circuits, pp. 65-93, 1979.

128

B. Meinerzhagen, K. Bach, I. Bork, and W. Engl, ``A New Highly Efficient Nonlinear Relaxation Scheme for Hydrodynamic MOS Simulations,'' in Proc. Intl. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, pp. 91-96, 1992.

129

T. Simlinger, R. Deutschmann, C. Fischer, H. Kosina, and S. Selberherr, ``Two-Dimensional Hydrodynamic Simulation of High Electron Mobility Transistors Using a Block Iterative Scheme in Combination with Full Newton Method,'' in Proc. Intl. Conf. Solid-State and Integrated Circuit Technology, pp. 589-591, 1995.

130

T. Grasser and S. Selberherr, ``Fully-Coupled Electro-Thermal Mixed-Mode Device Simulation of SiGe HBT Circuits,'' IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1421-1427, 2001.

131

B. Daniel, C. Parikh, and M. Patil, ``Modeling of the CoolMOS TM Transistor -- Part I: Device Physics,'' IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 916-922, 2002.

132

B. Daniel, C. Parikh, and M. Patil, ``Modeling of the CoolMOS TM Transistor -- Part II: DC Model and Parameter Extraction,'' IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 922-929, 2002.

133

J. Appels and H. Vaes, ``HV Thin Layer Devices (RESURF Devices),'' in Proc. Intl. Electron Devices Meeting, pp. 238-241, 1979.

134

F. Udrea and A. P. W. Milne, ``A New Class of Lateral Power Devices for HVIC's Based on the 3D RESURF Concept,'' in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, pp. 187-190, 1998.

135

F. Udrea and A. P. W. Milne, ``The 3D RESURF Junction,'' in Proc. Intl. Semiconductor Conf., pp. 141-144, 1998.

136

F. Udrea, T. Trajkovic, J. Thomson, L. Coulbeck, P. Waind, G. Amaratunga, and P. Taylor, ``Ultra-High Voltage Device Termination Using the 3D RESURF (Super-Junction) Concept - Experimental Demonstration at 6.5 kV,'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 129-132, 2001.

137

T. Fujihira, ``Theory of Semiconductor Superjunction Devices,'' Jpn. J. Appl. Phys., vol. 36, no. 10, pp. 6254-6262, 1997.

138

T. Fujihira and Y. Miyasaka, ``Simulated Superior Performances of Semiconductor Superjunction Devices,'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 423-426, 1998.

139

S. Xu, K. Gan, G. Samudra, Y. Liang, and J. Sin, ``120V Interdigitated-Drain LDMOS (IDLDMOS) on SOI Substrate Breaking Power LDMOS Limit,'' IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1980-1985, 2000.

140

J. Glenn and J. Siekkinen, ``A Novel Vertical Deep Trench RESURF DMOS (VTR-DMOS),'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 197-200, 2000.

141

R. Ng, F. Udrea, K. Sheng, K. Ueno, G. Amaratunga, and M. Nishiura, ``Lateral Unbalanced Super Junction (USJ)/3D-RESURF for High Breakdown Voltage on SOI,'' in Proc. Intl. Symp. Power Semiconductor Devices $\&$ Integrated Circuits, pp. 395-398, 2001.

142

Y. Zhu, Y. Liang, S. Xu, P.-D. Foo, and J. Sin, ``Folded Gate LDMOS Transistor With Low On-Resistance and High Transconductance,'' IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2917-2928, 2001.

143

S.-I. Liu, J.-F. Wei, and G.-M. Sung, ``SPICE Macro Model for MAGFET and its Applications,'' IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no. 4, pp. 370-375, 1999.

144

Y. Audet and G. Chapman, ``Design of a Large Area Magnetic Field Sensor Array,'' in Proc. Intl. Conf. Wafer Scale Integration, pp. 273-281, 1994.

145

J. Clark, ``CMOS Magnetic Sensor Arrays,'' in Solid-State Sensor and Actuator Workshop, pp. 72-75, 1988.

146

S. Sze, edited by, Semiconductor Sensors.
Wiley, 1994.

147

J. von Kluge and W. Langheinrich, ``An Analytical Model of MAGFET Sensitivity Including Secondary Using a Continuous Description of the Geometric Correction Factor $G$,'' IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 89-95, 1999.

148

L. Dang, ``A One-Dimensional Theory on the Effects of Diffusion Current and Carrier Velocity Saturation on E-Type IGFET Current Voltage Characteristics,'' Solid-State Electron., vol. 20, no. 10, pp. 781-788, 1977.

149

R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. LeBlanc, ``Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,'' Proc. IEEE, vol. 87, no. 4, pp. 668-678, 1999.

150

U. Çilingiroglu, Systematic Analysis of Bipolar and MOS Transistors.
Boston: Artech House, 1993.

151

R. Rios, R. Amantea, R. Smeltzer, and A. Rothwarf, ``Requirements for Accurate MOS-SOI Device Simulations,'' IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 581-586, 1992.

152

R. Stratton, ``Diffusion of Hot and Cold Electrons in Semiconductor Barriers,'' Physical Review, vol. 126, no. 6, pp. 2002-2014, 1962.

153

K. Blotekjaer, ``Transport Equations for Electrons in Two-Valley Semiconductors,'' IEEE Trans. Electron Devices, vol. ED-17, no. 1, pp. 38-47, 1970.

154

G. Baccarani and M. Wordeman, ``An Investigation of Steady-State Velocity Overshoot in Silicon,'' Solid-State Electron., vol. 28, no. 4, pp. 407-416, 1985.

155

M. Gritsch, H. Kosina, T. Grasser, and S. Selberherr, ``Revision of the Standard Hydrodynamic Transport Model for SOI Simulation,'' IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1814-1820, 2002.

156

Y.-C. Tseng, W. Huang, D. Monk, P. Welch, J. Ford, and J. Woo, ``AC Floating Body Effects and the Resultant Analog Circuit Issues in Submicron Floating Body and Body-Grounded SOI MOSFET's,'' IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1685-1692, 1999.

157

C. Edwards, W. Redman-White, B. Tenbroek, M. Lee, and M. Uren, ``The Effect of Body Contact Series Resistance on SOI CMOS Amplifier Stages,'' IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2290-2294, 1997.

158

Y. Taur, C. Wann, and D. Frank, ``25 nm CMOS Design Considerations,'' in Proc. Intl. Electron Devices Meeting, pp. 789-792, 1998.

159

Y. Taur, D. Buchanan, W. Chen, D. Frank, K. Ismail, S. Lo, G. Sai-Halasz, R. Viswanathan, H. Wann, S. Wind, and H. Wong, ``CMOS Scaling into the Nanometer Regime,'' Proc. IEEE, vol. 85, no. 4, pp. 486-504, 1997.

160

Y. Taur and E. Nowak, ``CMOS Devices below 0.1 $\mu$m: How High Will Performance Go?,'' in Proc. Intl. Electron Devices Meeting, pp. 215-218, 1997.

161

Y. Taur, ``CMOS Design Near the Limit of Scaling,'' IBM J. Res. & Dev., vol. 46, no. 2/3, pp. 213-222, 2002.

162

N. Lindert, L. Chang, Y.-K. Choi, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, ``Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process,'' IEEE Electron Device Letters, vol. 22, no. 10, pp. 487-489, 2001.

163

Y.-K. Choi, T.-J. King, and C. Hu, ``Nanoscale CMOS Spacer FinFET for the Terabit Era,'' IEEE Trans. Electron Devices, vol. 23, no. 1, pp. 25-27, 2002.

164

C. Auth and J. Plummer, ``A Simple Model for Threshold Voltage of Surrounding-Gate MOSFET's,'' IEEE Trans. Electron Devices, vol. 45, no. 11, pp. 2381-2383, 1998.

165

S. Cristoloveanu, F. Allibert, and A. Zaslavsky, ``Double-Gate MOSFETs: Performance and Technology Options,'' in Proc. Intl. Semiconductor Device Research Symposium, pp. 459-460, 2001.

166

J.-T. P. J.-P. Colinge and C. Diaz, ``Pi-Gate SOI MOSFET,'' IEEE Electron Device Letters, vol. 22, no. 8, pp. 405-406, 2001.

167

M. Kumar, H. Liu, and J. Sin, ``A High-Performance Five-Channel NMOSFET Using Selective Epitaxial Growth and Lateral Solid Phase Epitaxy,'' IEEE Electron Device Letters, vol. 23, no. 5, pp. 261-263, 2002.

168

X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, ``Sub-50nm P-Channel FinFET,'' IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880-886, 2001.

169

H.-S. Wong, ``Beyond the conventional transistor,'' IBM J. Res. & Dev., vol. 46, no. 2/3, pp. 537-570, 2002.

170

N. Lindert, Y.-K. C. L. Chang, E. Anderson, L. Wenchin, T. King, J. Bokor, and C. Hu, ``Quasi-Planar NMOS FinFETs with Sub-100 nm Gate Lengths,'' in Proc. Device Research Conf., pp. 26-27, 2001.

171

D. Fried, A. Johnson, E. Nowak, J. Rankin, and C. Willets, ``A Sub 40-nm Body thickness n-Type FinFET,'' in Proc. Device Research Conf., pp. 24-25, 2001.

172

N. Lindert, Y.-K.Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J.King, J. Bokor, and C. Hu, ``Quasi-Planar FinFETs with Selectively Grown Germanium Raised Source/Drain,'' in Proc. Intl. SOI Conf., pp. 111-112, 2001.

173

Y.-K. Choi, T.-J. King, and C. Hu, ``A Spacer Patterning Technology for Nanoscale CMOS,'' IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, 1991.

174

Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, ``Sub-20 nm CMOS FinFET Technologies,'' in Proc. Intl. Electron Devices Meeting, pp. 421-424, 2001.

175

Y.-K. Choi, T.-J. King, and C. Hu, ``Pacer FinFET: Nano-Scale CMOS Technology for the Terabit Era,'' in Proc. Intl. Semiconductor Device Research Symposium, pp. 543-546, 2001.

176

D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, ``FinFET--A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,'' IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000.

177

G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E.-C. Kan, ``FinFET Design Considerations Based on 3-D Simulation and Analytical Modeling,'' IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, 2002.

178

C. Petti, J. McVittie, and J. Plummer, ``Characterization of Surface Mobility on the Sidewalls of Dry-Etched Trenches,'' in Proc. Intl. Electron Devices Meeting, pp. 104-107, 1988.

179

E. Liu, C. Lin, X. Liu, and R. Han, ``Simulation of 100nm SOI MOSFET with FINFET structure,'' in Proc. Intl. Conf. Solid-State and Integrated Circuit Technology, pp. 883-886, 2001.

180

L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, ``Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,'' in Proc. Intl. Electron Devices Meeting, pp. 719-722, 2000.

181

X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, ``Sub-50nm FinFET: PMOS,'' in Proc. Intl. Electron Devices Meeting, pp. 67-70, 1999.

182

C. Wang and P.-F. Zhang, ``Three-Dimensional DIBL for Shallow-Trench Isolated MOSFET's,'' IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 139-144, 1999.

183

A. Mutlu and M. Rahman, ``Two-Dimensional Analytical Model for Drain Induced Barrier Lowering (DIBL) in Short Channel MOSFETs,'' in Proc. IEEE Southeastcon, pp. 340-344, 2000.