Introduction to Part III

It is likely that the scaling of CMOS device and process technology, as it is known today, will end by the 22 nm node (9 nm physical channel length) by 2016 [RO003], [Lun02], [Com01]. The grand challenge, then, is to invent and develop one or more new technologies that will extend the scaling of information processing technologies beyond 2016. It is important to understand that the emerging research devices are speculative, with no certainty of being implemented into manufacture.

Any new technology must extend microelectronics well beyond the domain of CMOS and should be interface-able with a CMOS platform [HBZB02], [RO001]. One candidate to complement CMOS in the long-term run is resonant tunneling with the use of RTD-FETs as novel logic devices. RTD device technology is now quite mature with many demonstrations of circuits [CMP03]. These are the first quantum transport devices to have made it into (pilot) production.

We see the simulation of RTDs as a test case for the simulation of quantum transport as is also needed for novel CMOS technology. Channel lengths or silicon films of a few nanometers cannot be accurately represented without (partially) ballistic transport models which also include quantum effects [BJSS04], [HWL04].

In scaled CMOS technology the short distance between source and drain requires a full two-dimensional quantum transport formulation [HWL04]. Several approaches have been suggested to realize these calculations. The simplest scheme is based on a self-consistent Poisson-Schrödinger coupled set of equations. A more advanced method is the quantum Liouville equation formulated in the Wigner function or in moments of the Wigner function leading to a quantum drift-diffusion model. Apart from the formal justification of the computational algorithm the CPU demands are also huge. These simulation methods were compared using the one-dimensional RTD as a testbed, where simulation costs are feasible.