2.6 Chemical Mechanical Polishing

Modern integrated circuits can have up to six wiring levels and this number is estimated to increase. If no means of planarization is used, the surface of the upper layers will be too rough. This will create several problems, being photolithography the most severe. As to decrease the minimum feature size, the imaging systems use higher and higher numerical aperture and consequently reduced depth of focus, the lithography of the upper layers becomes impossible (given that large design rules cannot obviously be allowed). One solution is to precede each metalization step by a planarization of the wafer. Chemical Mechanical Polishing (CMP) is gaining acceptance as a planarization technique. This consists of mechanically polishing the wafer in a chemical slurry with both etchant agents and abrasives. The difference as regards the plasma etching techniques described, is that unlike them, the damage is in CMP directed parallel to the wafer.