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Bibliography

1
G.E. Moore.
Cramming more Components onto Integrated Circuits.
Electronics, 38(8):114-117, April 1965.

2
Semiconductor Industry Association (SIA).
The National Technology Roadmap for Semiconductors.
San Jose, CA, 1997.

3
M.T. Bohr.
Interconnect Scaling - The Real Limiter to High Performance ULSI.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 241-244, 1995.

4
K. Roy, C. Chuang, S. Lu, K. Soumyanath, H. Partovi, and T. Sakurai.
Challenges for Low-Power and High-Performance Chips.
Design and Test of Computers, 15(3):119-124, July 1998.

5
S.Y. Oh and K.J. Chang.
2001 Needs for Multi-level Interconnect Technology.
Circuits and Devices Magazine, 11(1):16-21, January 1995.

6
J. Mar.
The application of TCAD in Industry.
In Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices - SISPAD'96, pp. 139-145, Tokyo, 1996.

7
A. Wu D. Gajski, N. Dutt and S. Lin.
High-Level Synthesis.
Kluwer Academic Publishers, 1994.

8
G. Massobrio and P. Antognetti.
Semiconductor Device Modeling with Spice.
McGraw-Hill, Second ed., 1993.

9
I. Pomeranz and S. Reddy.
On Diagnostics and Correction of Design Errors.
In Proc. Int. Conf. Computer-Aided Design - ICCAAD, pp. 500-507, 1993.

10
A.F. Schwarz.
Digital-Circuit Aspects and State of the Art, vol. II of Computer-Aided Design of Microelectronic Circuits and Systems.
Academic Press, 1987.

11
S. Kleinfeldt, M. Guiney, J.K. Miller, and M. Barnes.
Design Methodology Management.
Proc. IEEE, 82(2):231-250, February 1994.

12
G.E.P. Box and N.R. Draper.
Empirical Model-Building and Response Surfaces.
J. Wiley & Sons, 1987.

13
S. Halama, Ch. Pichler, G. Rieger, G. Schrom, T. Simlinger, and S. Selberherr.
VISTA--User Interface, Task Level, and Tool Integration.
IEEE Trans. Computer-Aided Design, 14(10):1208-1222, October 1995.

14
Ch. Pichler.
Integrated Semiconductor Technology Analysis.
Dissertation, Technische Universität Wien, March 1997.

15
G. Rieger.
Ein graphischer Editor für Entwurf von Halbleiterbauteilen.
Dissertation, Technische Universität Wien, 1996.

16
R. Plasun, M. Stockinger, R. Strasser, and S. Selberherr.
Simulation Based Optimization Environment and It's Application to Semiconductor Devices.
In Proc. Int. Conf. on Applied Modelling and Simulation - IASTED, pp. 313-316, Honolulu, Hawaii, USA, August 1998.

17
R. Lipsett, C. Schaefer, and C. Ussery.
VHDL: Hardware Description and Design.
Kluwer Academic Publishers, 1995.

18
F. Fasching, W. Tuppa, and S. Selberherr.
VISTA-The Data Level.
IEEE Trans. Computer-Aided Design, 13(1):72-81, January 1994.

19
G. Rieger, S. Halama, and S. Selberherr.
A Programmable Tool for Interactive Wafer-State Level Data Processing.
In Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices - SISPAD'95, pp. 58-61, Erlangen, Germany, 1995.

20
D.M.H. Walker, J.K. Kibarian, Ch.S. Kellen, and A.J. Strojwas.
A TCAD Framework for Development and Manufacturing.
In F. Fasching, S. Halama, and S. Selberherr, eds., Technology CAD Systems, pp. 83-112, Wien, 1993. Springer.

21
GDSII Stream Format.
Calma Corporation (now part of Cadence), San Jose, California, July 1984.

22
S.M. Rubin.
Computer Aids for VLSI Design.
Addison-Wesley Publishing Company, 1987.

23
C. Pichler, R. Plasun, R. Strasser, and S. Selberherr.
Simulation Environment for Semiconductor Technology Analysis.
In Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices - SISPAD'96, pp. 147-148, Tokyo, 1996.

24
D.M. Betz.
XLISP:An Object-Oriented Lisp.
Apple, Peterborough, New Hampshire, USA, 1989.

25
E.W. Scheckler, A.S. Wong, R.H. Wang, G. Chin, J.R. Camagna, K.K.H. Toh, K.H. Tadros, R.A. Ferguson, A.R. Neureuther, and R.W. Dutton.
A Utility-Based Integrated Process Simulation System.
IEEE Trans. Computer-Aided Design, 11(7):911-920, July 1992.

26
S. Wolf.
The Submicron MOSFET, vol. III of Silicon Processing for the VLSI Era.
Lattice Press, Sunset Beach, California, 1995.

27
A.R. Alvarez, B.L. Abdi, H.D. Weed, J. Teplik, and E.R. Herald.
Application of Statistical Design and Response Surface Methods to Computer-Aided VLSI Device Design.
IEEE Trans.Computer-Aided Design, 7(2):272-288, February 1988.

28
B.W. Kerningham and D.M. Ritchie.
The C Programming Language.
Prentice-Hall, 1988.

29
T. Brunner.
Pushing the Limits of Lithography for IC Production.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 9-13, 1997.

30
Y. Liu, A.K. Pfau, and A. Zakhor.
Systematic Design of Phase Shift Masks With Extended Depth of Focus and/or Shifted Focus Plane.
IEEE Trans. Semiconductor Manufacturing, 6(1):1-21, February 1993.

31
B.J. Lin.
Phase-Shifting Masks Gain and edge.
Circuits and Devices Magazine, 9(2):28-35, March 1993.

32
C. Sengupta, J.R. Cavallaro, W.L. Wilson, and F.K. Tittel.
Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations.
IEEE Trans. Semiconductor Manufacturing, 10(4):482-494, November 1997.

33
H. Kirchauer.
Photolithography Simulation.
Dissertation, Technische Universität Wien, March 1998.

34
H. Kirchauer and D. Selberherr.
Three-Dimensional Photolithographic Simulation.
IEEE Trans. Semiconductor Technology Modeling Simulation, (6), June 1997.
http://www.ieee.org/journal/tcad/.

35
E.A. Vittoz.
Design of Low-Voltage Low-Power IC's.
In Borel et al. [114], pp. 927-934.

36
R.H. Salters.
Low Voltage and Low Power Issues and Applications.
In Borel et al. [114], pp. 949-955.

37
M. Margala and N. Durdle.
Noncomplementary BiCMOS Logic and CMOS Logic for Low-Voltage, Low-Power Operation - A Comparative Study.
IEEE Trans. Computer-Aided Design, 33(10):1580-1585, October 1998.

38
A.P. Chandrakasan, S. Sheng, and R.W. Brodersen.
Low-Power CMOS Digital Design.
IEEE Trans. Computer-Aided Design, 27(4):473-484, April 1992.

39
N.H. Weste and K. Eshraghian.
Principles of CMOS VLSI Design.
Addison-Wesley Publishing Company, Second ed., 1993.

40
H.B Bakoglu.
Circuits, Interconnections, and Packaging for VLSI.
Addison-Wesley Publishing Company, 1990.

41
A.P. Chandrakasan and R.W. Brodersen.
Low Power Digital CMOS Design.
Kluwer Academic Publishers, 1995.

42
S.A. Campbell, D.C. Gilmer, X. Wang, M. Hsieh, H. Kim, W.L. Gladfelter, and J. Yan.
MOSFET Transistors Fabricated With High Permittivity TiO$_2$ Dielectrics.
IEEE Trans. Electron Devices, 44(1):104-109, January 1997.

43
Meta-Software Inc.
HSPICE User's Manual.
1996.

44
Y. Cheng, M. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko, and C. Hu.
A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation.
IEEE Trans. Electron Devices, 44(2):277-287, February 1997.

45
D.P. Foty.
MOSFET Modeling With SPICE: Principles and Practice.
Prentice-Hall, 1997.

46
N.D. Arora, R. Rios, C.L. Huang, and K. Raol.
PCIM: A Physically Based Bontinuous Short-Channel IGFET Model for Circuit Simulation.
IEEE Trans. Electron Devices, 41(6):988-997, June 1994.

47
M. Kondo, H. Onodera, and K. Tamaru.
Model-Adaptable MOSFET Parameter-Extraction Method Using an Intermediate Models.
IEEE Trans.Computer-Aided Design, 17(5):400-406, May 1998.

48
G. Schrom, A. Stach, and S. Selberherr.
An interpolation Based MOSFET Model for Low-Voltage Applications.
Microelectronics Journal, 29:529-534, 1998.

49
T. Simlinger, H. Kosina, M. Rottinger, and S. Selberherr.
MINIMOS-NT: A Generic Simulator for Complex Semiconductor Devices.
In H.C. de Graaff and H. van Kranenburg, eds., Proc. 25th European Solid State Device Research Conf. - ESSDERC'95, pp. 83-86, Gif-sur-Yvette Cedex, France, 1995. Editions Frontieres.

50
G. Scrom.
Ultra-Low-Power CMOS Technology.
Dissertation, Technische Universität Wien, June 1998.

51
A. Stach.
Simulation von MOSFET-Schaltungen.
Diplomarbeit, Technische Universität Wien, May 1995.

52
M. Lerme.
Multi-layer Metallization.
In Grünbacher [115], pp. 42-48.

53
E.M. Zielinski, S.W. Russel, R.S. List, A.M. Wilson, C. Jin, K.J. Newton, J.P. Lu, T. Hund, W.Y. Hsu, V. Cordesco, M. Gopikanth, V. Kosthnis, W. Lu, G. Cerny, N.M. Russel, P.B. Smith, S. O'Brien, and R.H. Havemann.
Damascene Integration of Copper and Ultra-Low-k Xerogel for High Performance Interconnects.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 936-938, 1997.

54
D. Lammers.
TI's 0.13-Micron Process Speeds System-On-a-Chip Designs.
EE-Times on-line, October 27th, 1998.

55
M. Miyamoto, T. Takeda, and T. Furusawa.
High-Speed and Low-Power Interconnect Technology for Sub-Quarter-Micron ASIC's.
IEEE Trans. Computer-Aided Design, 44(2):250-256, February 1997.

56
J.C. Rey, J.Li, V. Boksha, D. Adalsteinsson, and J.A. Sethian.
Topography Simulation for Interconnect Deposition.
Solid State Technology, pp. 77-82, February 1998.

57
T. Sakurai and K. Tamaru.
Simple Formulas for Two- and Three-Dimensional Capacitances.
IEEE Trans. Electron Devices, 30(2):183-185, February 1983.

58
E. Barke.
Line-to-Ground Capacitance Calculation for VLSI: A Comparison.
IEEE Trans. Computer-Aided Design, 7(2):295-298, February 1988.

59
J. Chern, J. Huang, L. Arledge, P. Li, and P. Yang.
Multilevel Metal Capacitance Models for CAD Design Synthesis Systems.
IEEE Electron Device Letters, 13(1):32-34, January 1992.

60
N.D. Arora, K.V. Raol, and L. M. Richardson.
Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits.
IEEE Trans. Computer-Aided Design, 15(1):58-67, January 1996.

61
U. Choudhury and A. Sangiovanni-Vincentelli.
Automatic Generation of Analytical Models for Interconnect Capacitances.
IEEE Trans. Computer-Aided Design, 14(4):470-480, April 1995.

62
S.Y Oh, K. Okasaki, J. Moll, O.S. Nakagawa, K. Rahmat, N. Chang, D. Hu, J. Chow, and W. Ho.
3D GIPER: Global Interconnect Parameter Extractor for Full-Chip Global Critical Path Analysis.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 615-618, 1996.

63
R.H. Uebbing and M. Fukuma.
Process-Based Three-Dimensional Capacitance Simulation-TRICEPS.
IEEE Trans. Computer-Aided Design, 5(1):215-220, January 1986.

64
J.P. Elliot, G.A. Allan, and A.J. Walton.
The Automatic Generation of Conformal 3D Data for Interconnect Capacitance Simulation.
In Proc. VLSI Multi-Level Interconnect Conference, pp. 664-666, June 1995.

65
K. Wang, F. Rotella, T. Chen, A. Lee, Z. Yu, R.W Knepper, J. Watt, and R.W. Dutton.
Layout-based Extraction of IC Electrical Behavior Models.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 209-212, 1994.

66
E. Strasser and S. Selberherr.
Algorithms and Models for Cellular Based Topography Simulation.
IEEE Trans. Computer-Aided Design, 14(9):1104-1114, September 1995.

67
W. Pyka, R. Martins, and S. Selberherr.
Efficient Algorithms for Three-Dimensional Etching and Deposition Simulation.
In Proc. Int. Conference on Simulation of Semiconductor Processes and Devices - SISPAD'98, pp. 16-19, Leuven, Belgium, 1998.

68
R. Sabelka, K. Koyama, and S. Selberherr.
STAP--A Finite Element Simulator for Three-Dimensional Thermal Analysis of Interconnect Structures.
In Proc. Simulation in Industry--9th European Simulation Symposium, pp. 621-625, Budapest, Hungary, 1997.

69
R.E. Bank.
PLTMG: A Software Package for Solving Elliptic Partial Differential Equations.
In Frontiers in Applied Mathematics, vol. 7, SIAM, Philadelphia, USA, 1990.

70
J.R. Shewchuk.
Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator.
In First Workshop on Applied Computational Geometry, pp. 124-133, May 1990.

71
S. Wolf.
Silicon Processing for the VLSI Era, vol. II.
Lattice Press, 1990.

72
A.H. Zemanian, R.P. Tewarson, C.P. Ju, and J.F. Jen.
Three-Dimensional Capacitance Computations for VLSI/ULSI Interconnections.
IEEE Trans. Computer-Aided Design, 8(12):1319-1326, December 1989.

73
A. Seidl, M. Svoboda, J. Oberndorfer, and W. Rosner.
CAPCAL - A 3D Capacitance Solver for Support of CAD Systems.
IEEE Trans. Computer-Aided Design, 7(5):549-556, May 1988.

74
Q. Ning, P.M. Dewilde, and F.L. Neerhoff.
Capacitance Coefficients for VLSI Multilevel Metalization Lines.
IEEE Trans. Electron Devices, 34(3):644-649, March 1987.

75
M. Mukai, T. Tatsumi, N. Nakauchi, T. Kobayashi, K. Koyama, Y. Komatsu, R. Bauer, G. Rieger, and S. Selberherr.
The Simulation System for Three-Dimensional Capacitance and Current Density Calculation with a User Friendly GUI.
Technical Report of IEICE, 95(223):63-68, 1995.

76
A.J. van Genderen and N.P. van der Meijs.
Using Articulation Nodes to Improve the Efficiency of Finite-Element Based Resistance Extraction.
In Proc. 33rd Design Automation Conference - DAC '96, pp. 758-763, June 1996.

77
R. Bauer, M. Stiftinger, and S. Selberherr.
Capacitance Calculation of VLSI Multilevel Wiring Structures.
In Proc. Int. Workshop on VLSI Process and Device Modeling - VPAD'93, pp. 142-143, 1993.

78
K. Nabors and J. White.
FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program.
IEEE Trans. Computer-Aided Design, 10(11):1447-1459, 1991.

79
M. Bächtold, J.G. Korvink, and H. Baltes.
Enhanced Multipole Acceleration Techniques for the Solution of Large Poisson Computations.
IEEE Trans. Computer-Aided Design, 15(12):1541-1554, December 1996.

80
Z. Wang, Y. Yuan, and Q. Wu.
A Parallel Multipole Accelerated 3-D Capacitance Simulator Based on an Improved Model.
IEEE Trans. Computer-Aided Design, 15(12):1441-1450, 1996.

81
Y.P. Coz, R.B. Iverson, H.J. Greub, P.M. Campbell, and J.F. McDonald.
Application of a Floating-Random-Walk Algorithm for Extracting Capacitances in a Realistic HBT Fast-RISC RAM Cell.
In Proc. Eleventh Int. VLSI Multilevel Interconnection Conference - VMIC, pp. 542-544, June 1994.

82
Technology Modeling Associates (now part of Avant!).
RAPHAEL Reference Manual.
Sunnyvale, California, 1997.

83
TEMPEST Manual.
Silvaco International, Santa Clara, California, 1997.

84
SOLIDIS Manual.
ISE AG, Zurich, Switzerland, 1997.

85
W. Neumueller, J. Alsmeier, G. Bronner, S. Ishibashi, and H. Klose.
DRAM Technology for Today's Market and Future DRAM Generations.
In Grünbacher [115], pp. 49-56.

86
S. Fujii et al.
A 45-ns 16-Mbit DRAM with Triple-Well Structure.
IEEE Trans. Computer-Aided Design, 24(5):1170-1175, 1989.

87
K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe.
Limitations and Challenges of Multigigabit DRAM Chip Design.
IEEE Journal of Solid-State Circuits, 32(5):624-634, May 1997.

88
D. Temmler.
Multilayer Vertical Stacked Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMs.
In Proc. Symposium on VLSI Technology, pp. 13-14, 1991.

89
D.H. Cho, Y.S. Eo, H.M. Seung, N.H. Kim, J.K. Wee, O.K. Kwon, and H.S. Park.
Interconnect Capacitance, Crosstalk, and Signal Delay for 0.35um CMOS Technology.
In Proc. Int. Electron Devices Meeting - IEDM, pp. 619-622, 1996.

90
D. Gardner, J. Meindl, and K. Saraswat.
Interconnection and Electromigration Scaling Theory.
IEEE Trans. Electron Devices, 34(3):633-643, March 1987.

91
J. Ramírez-Angulo, R. Geiger, and E. Sánchez-Sinencio.
Characterization, Evaluation, and Comparasion of Laser-Trimmed Film Resistors.
IEEE Journal of Solid-State Circuits, 22(6):1177-1189, December 1987.

92
R. Castelo, F. Montecchi, F. Rezzi, and A. Baschirotto.
Low-Voltage Analog Filters.
IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, 42(11):827-840, November 1995.

93
C.A. Laber and P.R. Gray.
A 20 MHz Sixth Order BiCMOS Parasitic-Insensive Continuous-Time Filter and Second Order Equalizer Optimized for Disk-Drive Read Channels.
IEEE Journal of Solid-State Circuits, 28(4):462-470, April 1993.

94
I.A. Young, J.K. Greason, and K.L. Wong.
PLL Clock Generator with 5 to 100 MHz of Locking Range for Microprocessors.
IEEE Journal of Solid-State Circuits, 27(11):1599-1607, November 1992.

95
Y.P. Tsividis and K. Suyama.
MOSFET Modeling for Analog Circuit CAD: Problems and Prospects.
IEEE Journal of Solid-State Circuits, 29(3):210-216, March 1994.

96
Q. Huang and M. Oberle.
A 0.5-mW Passive Telemetry IC for Biomedical Applications.
IEEE Journal of Solid-State Circuits, 33(7):937-946, July 1998.

97
E.S. Yang.
Microelectronic Devices.
McGraw-Hill, 1988.

98
M.J. Riezenman.
The Search for Better Batteries.
IEEE Spectrum, pp. 51-56, May 1995.

99
T.A. Duisters and E.C. Dijkmans.
A -90dB THD Rail-to-Rail Input Opamp Using a New Local Charge Pump in CMOS.
vol. 33, pp. 947-955, July 1998.

100
B.J. Hosticka, W. Brockherde, D. Hammerschmidt, and R. Kokozinski.
Low-Voltage CMOS Analog Circuits.
IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, 42(11):864-872, November 1995.

101
J.H. Huijsing AND R. Hogervorst AND K. de Langen.
IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, 42(11):841-852, November 1995.

102
G. Ferri and W. Sansen.
A 1.3V Op/Amp in Standard $0.7\mu m$ CMOS With Constant $g_m$ and Rail-to-Rail Input and Output Stages.
In Proc. IEEE Int. Solid-State Circuits Conference - ISSCC'96, pp. 382-383, 1996.

103
P.R. Gray and R.G. Meyer.
Analysis and Design of Analog Integrated Circuits.
Wiley, New York, Second ed., 1993.

104
LT1635 - 1.2 V MicroPower Op/Amp.
Linear Technology Corporation, Milpitas, California, 1998.

105
P.E. Allen, G.A. Rincon, and B.J. Blalock.
A 1V CMOS Op/Amp Using Bulk-Driven Mosfets.
In Proc. IEEE Int. Solid-State Circuits Conference - ISSCC'95, pp. 192-193, 1995.

106
Y.P. Tsividis.
Operation and Modeling of the MOS Transistor.
McGraw-Hill, 1988.

107
K. de Langen and J.H. Huijsing.
Compact 1.8V Low-Power CMOS Operational Amplifier Cells for VLSI.
In Proc. IEEE Int. Solid-State Circuits Conference - ISSCC'96, pp. 346-347, 1997.

108
J.F. Duque-Carrillo, R. Pérez-Aloe, and J.M. Valverde.
Biasing Circuit for High Input Swing Operational Amplifiers.
IEEE Journal of Solid-State Circuits, 30(2):156-159, February 1995.

109
J.F. Duque-Carrillo, R. Pérez-Aloe, and J.M. Valverde.
Constant-Gm Rail-to-Rail Common-Mode Range Input Stage With Minimum CMRR Degradation.
IEEE Journal of Solid-State Circuits, 28(6):661-667, June 1993.

110
R. Hogervost, J.P. Tero, R.G. Eschauzier, and J.H. Huijsing.
A compact Power-Efficient 3-V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries.
IEEE Journal of Solid-State Circuits, 29(12):1505-1512, December 1994.

111
K.R. Laker and W.M. Sansen.
Design of Analog Integrated Circuits and Systems.
McGraw-Hill, 1994.

112
J.E. Franca and Y. Tsividis.
Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing.
Prentice-Hall, Second ed., 1994.

113
R.G Eschauzier, R. Hogervorst, and J.H. Huijsing.
APprogrammable 1.5 V CMOS Class-AB Amplifier With Hybrid Nested Miller Compensation for 120 dB Gain and 6 MHz UGF.
IEEE Journal of Solid-State Circuits, 29(12):1497-1504, December 1994.

114
J. Borel, P. Gentil, J. Noblanc, A. Nouailhat, and M. Verdone, eds.
Proc. 23rd European Solid State Device Research Conference - ESSDERC'93. Editions Frontieres, 1993.

115
H. Grünbacher, ed.
Proc. 27th European Solid State Device Research Conference - ESSDERC'97. Editions Frontieres, 1997.



Footnotes

...
All dissertations from the Institute for Microelectronics, Technical University Vienna, Vienna, Austria are available on the WWW at http://www.iue.tuwien.ac.at/.


Rui Martins
1999-02-24