Subsections

• 6.3.1 Proximity Correction of Masks
• 6.3.2 Integrating an EEPROM Module into a State-of-the-Art Silicon Foundry Process with Three-Dimensional TCAD
  • 6.3.2.1 Introduction
  • 6.3.2.2 EEPROM Module Integration
  • 6.3.2.3 EEPROM Cell Optimization
  • 6.3.2.4 Conclusions
  
  
• 6.3.3 Generation of 3D-Mask Photo Resist Shape for lateral PIN-Diodes

6.3 Layout and Mask Generation

Based on the principles shown in Section 2.4 some examples for proximity correction of masks and possible applications are given in the following sections.

6.3.1 Proximity Correction of Masks

The proximity correction of masks may be of importance, if structure sizes approach the wavelength of the lithography system. At the 350nm node this is the case for the ``Gate'' mask, the ``Active Area'' mask, the ``Contact'' mask and the ``Metal 1'' mask. However in normal TCAD applications the proximity effects of these masks are not taken into account, because the typical critical dimensions of the front end masks (``Active Area'' and ``Gate'' which are have the main impact on the device characteristics) are well controlled and are well calibrated in the TCAD simulations. The back end masks are only interesting for generating the contacts on top of the device. The detailed interconnect shape is not of interest for routinely TCAD simulations. However, in the application area of RF and high voltage, the exact interconnect shape is influencing the analysis strongly in certain aspects. The equivalent RLC network of the digital interconnect may impact the overall switching speed strongly (at least at ground rules below 180nm) [156],[157],[158]. For high voltage ultra low ohmic driver arrays with on-resistances in the milliohm range, the metalization resistance is contributing more than 50% to the total on-resistance.
These examples show, that an exact shape of the interconnect wires may impact the overall simulation result quite strongly. To obtain structures to analyze these influences more thoroughly with simulation, first a proximity corrected layout has to be generated. The detailed physics behind the generation of the corrected layout was described already in Chapter 2. For the following examples a modified version of LAYGRID [159],[160], the structure generator for the finite element electro-thermal simulation tool SAP [161],[162],[163] was used. The modification included the implementation of the aerial image simulator LISI developed by Heinrich Kirchauer [44] into the LAYGRID software. The original (mask biased) CIF file was taken together with the parameters of the lithography system (aperture etc.) as outlined in [164] and [165] and submitted to the modified LAYGRID code. The implemented LISI code generated a contour of every layer in the CIF file comprising of the light intensities at the surface of the photo resist (the aerial image). To obtain a fast and efficient simulation methodology the complicated and time consuming calculation of the exact photo resist shape after exposure and development was neglected. A certain threshold of the illumination intensity of the aerial image was chosen and the iso-contours of this intensity were extracted from the aerial image. This threshold was chosen to match the width of the final CDs of isolated mask lines accordingly. The contours were then written back into CIF file for further processing. The resulting CIF format can be used by any commercial or university TCAD simulator for further processing (e.g. process simulation). Examples for two digital cells (an inverter and a bigger digital cell comprising of 22 CMOS transistors) are shown in Figure 6.6 and Figure 6.7.

Figure 6.6: Initial layout of a digital inverter structure (a), contour plots of intensity distribution during the illumination of photo resist at different levels (b)-(e) and resulting resist contours after development (f)

$\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_layout.ps}\\ \centering (a)}$     $\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_AA.ps}\\ \centering (b)}$     $\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_P1.ps}\\ \centering (c)}$     $\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_CO.ps}\\ \centering (d)}$     $\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_M1.ps}\\ \centering (e)}$     $\parbox{0.20\textwidth}{ \includegraphics[width=0.20\textwidth]{figures/inverter_M1.ps}\\ \centering (f)}$

Figure 6.7: Initial layout of a big digital cell structure, contour plots of intensity distribution during the illumination of photo resist at different levels and resulting resist contours after development

$\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_layout.ps}\\ \centering (a)}$ $\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_AA.ps}\\ \centering (b)}$ $\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_P1.ps}\\ \centering (c)}$

$\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_CO.ps}\\ \centering (d)}$ $\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_M1.ps}\\ \centering (e)}$ $\parbox{0.3\textwidth}{ \includegraphics[width=0.3\textwidth]{figures/big_cell_contours.ps}\\ \centering (f)}$

The resulting mask information was used to generate a three dimensional representation of the interconnect structures of the big digital cell with LAYGRID. A comparison of the metalization, and gate lines with and without proximity correction is given in Figure 6.8.

Figure 6.8: Comparison of the interconnect shape of a three-dimensional structure of a big digital cell (a) with and (b) without proximity correction

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This structure can be used for further analysis of capacitance coupling, extraction of the RLC components of the interconnect or the overall metalization resistance.

6.3.2 Integrating an EEPROM Module into a State-of-the-Art Silicon Foundry Process with Three-Dimensional TCAD

6.3.2.1 Introduction

Non-volatile memories (NVM) [166],[167],[168] play an important role in modern System-on-a-Chip (SoC) solutions. The increasing demand of user-programmable information in such systems has led to new challenges in designing circuits with a certain amount of memory. NVMs are typically used in mobile, small systems for flexible applications which require variable information storage.
A variety of NVMs is available, each having different specifications according to the structure of the selected cell. A comprehensive overview is given in [169]. Two different programming principles can be identified, hot-electron injection (HEI) [170] and FOWLER-NORDHEIM (FN) tunneling [171],[172]. This work concentrates on an architecture that uses FN tunneling as the programming mechanism. This EEPROM cell was developed by J.M. Caywood [173],[174] and combines good endurance and reliability with a simple structure and good performance with average area consumption.

6.3.2.2 EEPROM Module Integration

The EEPROM p-channel memory cell was implemented in a common 0.35$\mu m$ CMOS process flow. The front-end-process flow is presented in Figure 6.9. The detailed schematics for the EEPROM process module steps may be found elsewhere [174].

Figure 6.9: Block diagram of the front-end silicon foundry process flow

Three ``flavors'' of the cell were evaluated. The implemented version makes use of a thick SiO$_2$ dielectric between the floating gate and the control gate (see Figure 6.10). Two other possibilities are a full ONO-stack as dielectric [175], or ONO between the control gate and the floating gate and SiO$_2$ for the control transistors [173].

Figure 6.10: Comparison of the three different EEPROM cell architectures (a) Full ONO Cell, (b) ONO-Spacer Cell, (c) Full Oxide Cell

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Several implications arise for integrating an EEPROM memory in a CMOS process. First, the programming and erasing operation requires voltages up to 15V, which are normally far above the breakdown voltage of the S/D junctions (this is the case for technology nodes below 0.6$\mu m$ and gets more severe for state-of-the-art nodes e.g. 130nm and beyond). Second, the added complexity of the overall process flow must not increase to a level where dual-chip packaging are cheaper solutions. As a consequence a maximum of only 2-4 additional mask alignments are acceptable. Third, the thermal budget of the high-voltage gate oxide for the control-gates will disturb sensitive threshold adjust implants and must therefore be placed before them. Fourth, for EEPROM memory operations additional high voltage devices are necessary to enable the generation of the programming voltage via charge pumps and to switch these voltages for the cell programming and erasing. As a consequence of these constraints the EEPROM-module must be integrated after the steps with the high thermal budget (e.g. the well diffusions) and before the sensitive threshold adjust and LDD steps which determine the standard CMOS logic. Since the base CMOS process offers already a dual gate (3.3V and 5V) analog mixed-signal option, the integrated flow includes three gate oxides. The HV-gate oxide of the cell is integrated right before the 3.3V and 5V gate oxides (refer to Figure 6.9). To get a deeper insight into the integration challenges, TCAD (Technology Computer Aided Design) simulations were used to find the best solution for the EEPROM module integration. Furthermore, the cell characteristics were optimized and the prediction of the electrical characteristics was used to generate preliminary SPICE models of the cell. This enabled a very early start of the memory block design. Additionally the transient behavior of the cell in programming operation was evaluated by TCAD.

6.3.2.3 EEPROM Cell Optimization

To predict the EEPROM cell behavior two main areas of operation had to be investigated.
The accuracy of the DC characteristics of the cell is mainly determined by the overall calibration of the TCAD environment. Since this calibration was performed with the CMOS base process, the first results were already quite accurate.
The transient programming characteristics however, showed significant deviations from literature data [174]. The cause for these differences were inaccurate FN-tunneling model parameters in the device simulator DESSIS-ISE [83]. The most used model to describe tunneling is the FOWLER-NORDHEIM equation [176]

$$J= A \ensuremath{E_\mathrm{diel}}^2 \exp \left( -\frac {B} {\ensuremath{E_\mathrm{diel}}} \right)$$ (6.2)

which was originally intended to describe tunneling between metals under intense electric fields. The parameters A and B have been refined by LENZINGER and SNOW [177]:

$$J= \frac {\ensuremath {\mathrm{q}}^3\ensuremath{m_\mathrm{eff}}} ... ...})^3}} {3\hbar \ensuremath {\mathrm{q}}\ensuremath{E_\mathrm{diel}}} \right) .$$ (6.3)

This equation is the preferred model in the device simulator DESSIS-ISE. A comprehensive description of the tunneling mechanisms in semiconductors is given in [178]. The results of the calibrated model and the comparison to measurements are shown in Figure 6.11. The differences between the measurements and simulation are caused by the assumptions in (6.3), namely zero temperature, a triangular energy barrier, and equal materials on both sides of the dielectric. Nevertheless, this model is chosen on default to ensure stability and good convergence behavior in the TCAD device simulation.

Figure 6.11: Comparison of simulated and measured tunnel currents through the tunneling oxide

The measurements were carried out on structured wafers with the tunnel oxide and a simple dot-masked polysilicon layer on top. The polysilicon dots were contacted with one needle of a micromanipulator, and the voltage between this contact and the wafer-chuck was varied appropriately.
One key parameter of an EEPROM cell using FN-tunneling is programming speed. Since the tunneling current density and therefore the programming time of the floating gate depends exponentially on the applied potential, c.f. (6.3) the gate coupling ratio[172]:

$$\alpha_g = \frac{\delta V_{FG}}{\delta V_{CG}} = \frac{C_{PP}}{C_{tot}} = \frac{C_{PP}}{C_S+C_{SUB}+C_D}$$ (6.4)

is the major contributor to cell speed. In order to optimize the cell speed, the Control-Gate/Floating Gate Capacitance $C_{pp}$ must be maximized. Figure 6.12 shows all contributions to the coupling ratio.

Figure 6.12: Capacitive equivalent circuit of the EEPROM cell

The coupling ratio of the EEPROM cell is already excellent, since the special layout [174] enables an encapsulation of the floating-gate by the control-gate on all sides. The main parameter left for increasing the coupling-ratio is the thickness of the floating gate. However, there is a tradeoff between floating gate thickness, step-coverage, and minimum cell distance in a memory block.
Using three-dimensional TCAD-process- and device-simulations a parameter optimum, matching the measurements, was found. Furthermore, the coupling-ratio of the cell itself could be predicted. The process simulation was again calibrated by comparing the three-dimensional TCAD boundary model with SEM pictures taken during fabrication (Figure 6.13).

Figure 6.13: EEPROM cell after floating-gate mask etch (a)Three-dimensional TCAD process simulation (b) SEM photograph of real structure

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The final structure of the EEPROM cell obtained by three-dimensional process simulation, which serves as input for a finite element analysis [162] for the extraction of the capacitances and the coupling-ratio, is shown in Figure 6.14.

Figure 6.14: Structure of the EEPROM memory cell generated by three-dimensional process simulation (one quarter of the cell is shown)

The process simulation was performed by combining the simulation tools DIOS-ISE [82] and TOPO3D [179] [180]. The formation of the field oxide was carried out by a two-dimensional simulation performed with DIOS-ISE. Due to the three-dimensional nature of the problem, switching to a full three-dimensional analysis is required, beginning with the formation of the floating gate. Therefore the two-dimensional structure generated by DIOS-ISE was expanded to a three-dimensional geometry representation. In the following an isotropic deposition of the poly-silicon layer was performed with TOPO3D which is a rigorous three-dimensional simulator for etching and deposition processes. In order to transfer the floating gate mask, an etching model of TOPO3D was applied, which is capable of taking aerial image information into account. The aerial image figure of the floating gate mask was produced by the aerial image simulator LISI [181],[182],[183] and loaded into the topography simulator. Worth mentioning is that the mask information for the aerial image simulation is taken from a gds2-file containing a 3$\times$3 cell array to prevent disturbances because of simulation domain boundaries (Figure 6.15).

Figure 6.15: Aerial image simulation result of the floating gate mask of a 3$\times$3 EEPROM cell array [181].

By this single process simulation step, five real process steps (mask deposition, mask illumination, mask development, anisotropic polysilicon etching and mask removal) are approximated in order to save computation time (without loosing significant accuracy as shown in Figure 6.13.
Subsequently (the doping formation steps are neglected, since they do not significantly impact the coupling ratio) the dielectric (SiO$_2$) between the floating gate and the control gate is grown. This oxidation process is approximated by an isotropic deposition step in the simulation analysis and is performed with TOPO3D as well, in order to avoid a full three-dimensional oxidation simulation.
For the formation of the control gate equivalent simulation steps as for the formation of the floating gate were used. The simulation is finalized by deposition of a thick layer of silicon dioxide, which prevents against disturbances in the capacitance extraction due to boundary effects.
The extracted capacitance values (listed in Table 6.2) give a gate coupling ratio of $\alpha_g = C_{PP} / (C_{Sub} + C_{PP} + C_S + C_D)$ = 72.4 % (refer also to Figure 6.12 and (6.4)) which is in good agreement with measurements based on the algorithms given in [172].

Table 6.2: Extracted capacitances within the EEPROM memory cell

$C_{PP}$	Control G. $\leftrightarrow$ Floating G.	2.38$\cdot$10$^{-15}$F
$C_{Sub}$	Floating G. $\leftrightarrow$ Substrate	5.69$\cdot$10$^{-16}$F
$C_S+C_D$	Control G. $\leftrightarrow$ Substrate	3.37$\cdot$10$^{-16}$F

6.3.2.4 Conclusions

TCAD methods are nowadays the method of choice for add-on module process integration. It was demonstrated that predictions for some technology key performance indicators can be derived. This methodology is excellently suited for a successful, timely and cost effective implementation of non-standard modules into a base process flow. In special cases three-dimensional process simulation is already feasible for industrial use.

6.3.3 Generation of 3D-Mask Photo Resist Shape for lateral PIN-Diodes

This example deals with the coupled process and device simulation of a laterally diffused PIN-diode of special shape and subsequent comparison of the device simulation results to electrical measurements. Furthermore, it gives an outlook to layout optimization of laterally diffused devices in general. This example is one of the first fully integrated process and device simulations including non-Manhattan type structures and full incorporation of lithography proximity effects on photo resist level. Previous work was constrained to Manhattan type ( $90 ^\circ$ angles between boundary primitives) structures without taking into account rigorous lithography simulation. By applying this new methodology significant differences in electrical characteristics between two-dimensional and three-dimensional simulations have been obtained. The simulated device was a Zener-diode in a $350nm$ CMOS technology process. This relatively "big" technology process was chosen to demonstrate the impact of three-dimensional effects in device characteristics even in such "old" process technologies. The layout of the element is of inherent two-dimensional nature because of the $45 ^\circ$ angles in the p+ and n+ doped regions of the device. A complete process flow was simulated (see Figure 6.16) including the following critical steps:

1. Starting with two-dimensional process simulation up to the first critical two-dimensional lithography mask
2. Interfacing into three-dimensions by sweeping the structure laterally (see Figure 6.17)
3. Three-dimensional lithography simulation including simulation of resist exposure and development (see Figure 6.18)
4. Three-dimensional Monte-Carlo implantation (see Figure 6.19 (a))
5. Rapid-Thermal-Annealing
6. Mesh-refinement with respect to the metallurgical-junctions and the counter doped I-region of the PIN-diode
7. Placement of the metal contacts on top of the structure (see Figure 6.19 (b) )

After Step 7 the simulation ends with a mesh representation of the final device including the three-dimensional doping distribution of the lateral PIN-diode (see Figure 6.19 (c)). To examine the difference between the two-dimensional simulation and the three-dimensional case, an additional two-dimensional process simulation was carried out up to contact deposition.

Figure 6.16: Schematic flow for coupled three-dimensional process and device simulation

Figure 6.17: Two-dimensional initial structure and resulting three-dimensional mesh after conversion into three dimensions

Figure 6.18: (a)SC-TOP simulation of ASM implantation mask shape (b)SC-TOP simulation of BSM implantation mask shape

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Figure 6.19: Generation of Zener diode mesh suitable for device simulation (a)Device after successive P+ and N+ Implantations using photo resist masks shown in Figure 6.18 (b)Boundary from interconnect simulation using SC-TOP for placement of the contacts (c)Final PIN-diode structure with merged contacts on top (ready for device simulation)

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Figure 6.20: Comparison of two-dimensional and three-dimensional device simulation results with measured characteristics of PIN-diode

For the three-dimensional diode it turned out that phonon-assisted band-to-band tunneling cannot be neglected. In this steep pn-junction this effect is crucial to reproduce the measured reverse characteristics of this diode. The model had to be switched on, when the electric field in some regions of the device, exceeded approx. $8 \times 10^5$ V/cm. The band-to-band tunneling is modeled using the expression from SCHENK [184]. The results given in Figure 6.20 show clearly that this PIN-diode is a true three-dimensional device which cannot be simulated in two dimensions. The two-dimensional simulation predicts the breakdown voltage far too high (about 25 %) compared to measurements. The result of the three-dimensional analysis is in excellent agreement with the measured data. Figure 6.21 shows the resulting doping distribution after process simulation and its potential distribution after device simulation during onset of breakdown. In addition, due to the three-dimensional shape of the electric field inside the active region of the Zener-diode and the field peaks located at the border of the overlapping diffusions (see Figure 6.22), the tunnel current below breakdown is predicted about 4 decades to small compared to 3D results and the measurements.

Figure 6.21: Doping (a) and (b) and potential (c) and (d) distribution inside the zener structure

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Figure 6.22: Electrical field distribution inside zener structure, (a) field distribution, (b) contour plots, (c) iso-surface at 0.25 MV/cm, (d) iso-surface at 0.6 MV/cm

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