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Subsections


6.5 Using TCAD with SPC

6.5.1 Introduction

A semiconductor fabrication process consists of several hundred unit process steps, each of which is subject to potential misprocessing. Such misprocessing typically occurs when wrong tool recipes are loaded and executed, or process steps are accidentally left out or performed twice. Although many of these issues are immediately detected at the next process step because of the physical deviation of the wafers from their usual appearance, some of these misprocessed wafers make their way through the whole production line and the failure is only detected at electrical parameter test. In such cases it is paramount that the cause of the failure is identified as quickly as possible to prevent other wafers in the fabrication line from being misprocessed the same way.
One special group of unit processes that is of particular interest in this context is the group of implant steps. Advanced semiconductor process flows contain several dozens of different implant steps, and since the implants do only affect the electrical, but not the mechanical or optical properties of the semiconductor wafers, a missing or double implant will typically be detected only at electrical test. Although large efforts have been made to prevent implant accidents, a certain risk remains in every not fully automated semiconductor fabrication facility.
Unfortunately, the relationship between the implants performed and the electrical behavior of the semiconductor devices is of high complexity, and the inference from the electrical data obtained at test to what actually happened during production requires the judgment and experience from device engineering experts.
In the following an approach is shown, how this inference can be made by a broader range of personnel with an even higher level of certainty.
During recent years, simulation techniques for semiconductor processing have been developed at a breathtaking speed. It is therefore feasible today, to feed a process flow, including all relevant process parameters, into a TCAD simulation, thereby creating a virtual semiconductor device such as a typical transistor, and extract the electrical properties of this simulated device. Parameters such as thresholds, saturation currents, sheet resistances or similar can thus be calculated for almost any given process flow.
So far, TCAD simulation has been extensively used for process development, but its application for manufacturing control and corrective action was very limited, which is partly due to the fact that its application needs skilled specialists. The advantages, of running a complete set of TCAD simulations of a transistor device for the process of record (POR), and for all process flows that result from both, an accidental missing and double implant (for each implant step), are described in the following sections.

6.5.2 Computational Effort

The current work is based on the analysis of austriamicrosystems' $ 0.35\mu m$ CMOS-mixed-signal process licensed from TSMC. This industry standard process offers two different gate oxide options (3.3V and 5V) resulting in 4 basic CMOS devices.
Performing a full factorial simulation of only 3 parameters (p-well, n-well and PMOS threshold adjust implant) with parameter values 0,1,2 (corresponding missing, correct and double implants) takes $ 3^3 = 27$ different simulation runs. Because of speed and memory constraints only one CMOS-transistor can be simulated per run, 108 different runs have to be executed to get the full information for these three implants on four transistors. This took a full weekend on a cluster of four 2GHz Linux computers, but having these data calculated up front, enables an engineer to identify very quickly the step where misprocessing occurred, in case a lot fails at electrical parameter test. Furthermore, this information has to be calculated only once, since these data reflect the situation in a frozen process flow.

6.5.3 Selecting a Set of Parameters

Since this $ 0.35\mu m$ process contains 16 implants in total, it is obvious that a full factorial computation is not feasible as the number 4096 of required simulation runs for a full factorial design exceeds all reasonable computation efforts.
However, it is neither necessary nor sensible to do a full factorial design, because, as the probability for a process incident is rather small, the probability that multiple implant steps have been misprocessed is vanishing. However, it is not sufficient to calculate only the 32 situations for each single implant step being skipped or doubly processed, because scenarios where a wrong implant recipe is used lead to situations where one implant is missing and another one doubled. Hence, the possible combinations of missed and double implants have to be selected carefully. So, as can be seen from Table 1, out of the possible 27 combinations only 1 (process of record) + 3 times 2 (missing and double implant each) + 2 (swapped P- and N-Well implants) = 9 combinations remain that make sense.
Furthermore, one can distinguish between different implant "classes" which affect only certain electrical parameters. E.g., incidents related to the standard polysilicon resistor implant (poly 2 implant) can be easily detected by measurement of the polysilicon resistance. Hence, only three TCAD calculations need to be performed to cover possible incidents at this particular implant step.
This leads to the general requirement that some efforts are needed to identify an appropriate set of electrical parameters which will give an unambiguous indication of the "culprit" implant.

6.5.4 Simulation Results

The parameter values were extracted from combined process- and device simulations with the Synopsys software suite. Each step of the process flow relevant for the device structures was taken into account for the process simulation. After coming up with a device structure as shown in Figure 3.9 a device simulation was performed to obtain device characteristics like saturation current or NMOS threshold. The identical parameter extraction algorithms as in actual electrical tests were applied to enable a comparison to measured values for calibration of the simulation. Finally, the relative deviation of the nominal electrical parameters was calculated the results of which are shown in Table 6.4.

Table 6.4: Calculated differences of the selected parameters to the nominal implant set (1,1,1) in percent
Implant NMOS3V PMOS3V NMOS5V PMOS5V
N-Well P-Well $ V_{TH}$ $ I_{DS}$ $ V_{TH}$ $ I_{DS}$ $ I_{DS}$ $ V_{TH}$ $ I_{DS}$
1 1 1 0% 0% 0% 0% 0% 0%
1 1 0 0% 0% -52% 0% 0% -61%
1 1 2 0% 0% 66% 0% 0% 110%
1 0 1 6% -9% 0% 12% -20% 0%
1 2 1 -2% 9% 0% -11% 24% 0%
0 1 1 0% 0% 15% 0% 0% 39%
0 2 1 -2% 9% 15% -11% 24% 39%
2 1 1 0% 0% -17% 0% 0% -17%
2 0 1 6% -9% -17% 12% -20% -17%


These results show clearly the power of the proposed method for identifying root causes for wafer misprocessing. By choosing the driving capability and the threshold voltage of two different types of NMOS and the driving capability of two different types of PMOS transistors an unabigous set of electrical parameters was obtained. The percentage values in the table are relative changes of the parameters compared to the typical situation indicated in the first line of the table.

6.5.5 Conclusions

It has been shown that the proposed method has the power to identify root causes for wafer misprocessing quickly. Before the development of this method, it took valuable time of PCM data analysis by an experienced device engineer to find switched PLDD and NLDD reticles as the root cause for a misprocessed lot.
As these kinds of implant misprocessing incidents are rare, the system has to be understood as a preventive method to react to such problems as quickly as possible. It can save both, expensive engineering resources and additional measurements. Furthermore, the system can be used to rule out a number of speculations by simply trying them out with simulation and compare the "fingerprint" of their results.


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Next: 7. Summary and Outlook Up: 6. Industrial Application of Previous: 6.4 Inverse Modeling of

R. Minixhofer: Integrating Technology Simulation into the Semiconductor Manufacturing Environment