4.2.3.2 On-State Characteristics

The on-state characteristics of the lateral trench gate SOI-LDMOSFET have been analyzed with a negative back-gate bias. The drain current in the quasi-saturation region is determined by the current conduction in the $ n$-drift region. Increased negative back-gate bias causes the reduction of the conduction area at the drift region.

As can be seen in Figure 4.20 the threshold back-gate voltage exists at the back-gate bias $ V_\mathrm{BS}$ $ =$ $ -40$V. If the back-gate bias is more negative than this value [156,157], the hole inversion can be seen on the top of the buried oxide. The drain current remains almost constant below the threshold back-gate bias. This effect is similar to that of the conventional high-voltage SOI-LDMOSFET. For a back-gate bias of 0V, most of the $ n$-drift region conducts current (Figure 4.21). With a negative back-gate bias the depletion edge moves upwards (Figure 4.21), and the drain current is reduced.

Figure 4.20: On-state characteristics of the lateral trench gate SOI-LDMOSFET at $ V_\textrm {GS}$ $ =$ 12 V and $ V_\textrm {BS}$ $ =$ 0 V, $ -20$ V, $ -40$ V, $ -60$ V.
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Figure 4.21: Electron concentration in the lateral trench gate SOI-LDMOSFET at $ V_\textrm {GS}$ $ =$ 12 V, $ V_\textrm {DS}$ $ =$ 10 V, and $ V_\textrm {BS}$ $ =$ 0 V. The dark area shows a high electron concentration.
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Figure 4.22: Electron concentration in the lateral trench gate SOI-LDMOSFET at $ V_\textrm {GS}$ $ =$ 12 V, $ V_\textrm {DS}$ $ =$ 10 V, and $ V_\textrm {BS}$ $ =$ $ -60$ V. Suppressed electron concentration (reduced dark area compared to Fig. 4.21) can be seen because of the negative substrate bias.
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Figure 4.23: Specific on-resistance of the conventional and the lateral trench gate SOI-LDMOSFETs at $ V_\textrm {GS}$ $ =$ 12 V and $ V_\textrm {DS}$ $ =$ 0.5 V.
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Figure 4.23 and Table 4.2 show a comparison of the on-state characteristics of a conventional and a lateral trench gate SOI LDMOSFET. From this figure it becomes clear that the lateral trench gate SOI-LDMOSFET has enhanced current handling capability. $ R_\mathrm{sp}$ rapidly decreases with increasing trench depth, but it weakly depends on the space between the trenches. With a trench depth of 0.5$ \mu $m and a space between the trenches of 0.5$ \mu $m, $ R_\mathrm{sp}$ has a similar value to that of a conventional device. With a trench depth of 1.5$ \mu $m, the $ R_\mathrm{sp}$ of the device is 264m$ \Omega$ mm $ ^\mathrm{-2}$ at $ V_\mathrm{GS}$ $ =$ 12V and $ V_\mathrm{DS}$ $ =$ 0.5V. Even for the devices with a BV over 100V the contribution of the $ n$-drift resistance is dominant in the on-resistance. A further reduction of the on-resistance is achieved by increasing the channel area with the proposed device.

The on-resistance of the proposed device is about 8.3% smaller than the corresponding $ R_\mathrm{sp}$ value of the conventional SOI-LDMOSFET (about 288m$ \Omega$ mm $ ^\mathrm{-2}$).



Table 4.2: DC performance comparison between the conventional and the lateral trench gate SOI-LDMOSFET.
  Conventional LDMOSFET on SOI Lateral trench gate SOI-LDMOSFET
$ N_\mathrm{D}$ 1.0 $ \times $ $ 10^{16}$ $ \mathrm{cm}^{-3}$ 1.0 $ \times $ $ 10^{16}$ $ \mathrm{cm}^{-3}$
$ L_\mathrm{d}$ 5.5$ \mu $m 5.5$ \mu $m
$ R_\mathrm{sp}$ 288m$ \Omega$ mm $ ^\mathrm{-2}$ 264m$ \Omega$ mm $ ^\mathrm{-2}$
BV 112V 117V

Jong-Mun Park 2004-10-28