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9.1 Standard CMOS Process

 

To demonstrate the application of the VISTA/SFC environment to the modeling and analysis of VLSI fabrication processes, a complete standard silicon-gate LOCOS CMOS process [SS91] was simulated using a set of heterogeneous simulation tools. The process flow contains all types of fabrication process steps occurring in modern VLSI technology and uses eleven lithography masks. Simulation was carried out up to the second metalization layer, which forms the gate lines, using 55 tool steps. The simulated structure is a CMOS inverter, containing most of the relevant intrinsic and parasitic devices. The final topography is shown in Figure 9.1. An overview of the process is given in Table 9.1, a detailed description can be found in [SS91], p. 370.  

 figure2483
Figure 9.1:   The final CMOS structure including two metal layers.

To achieve accurate and realistic modeling of etching and deposition processes, the PROMIS etch module [SS93] [SS95] was used. It is based on extremely stable cell-based algorithms and contains a number of physically sound models for a variety of topography processes. Lithography steps are performed by the SKETCH tool which operates as a simple geometry manipulator and provides mask pattern transfer and material strip capabilities where no accurate simulation of optical phenomena is needed. All implantation steps have been carried out with the PROMIS implantation module [Sti93] [Boh96]. Diffusion has been realized with the PROMIS-NT diffusion module [PS95] [Puc96], which offers the possibility of solving different models on each material segment and therefore greatly facilitates the investigation of advanced effects in state-of-the-art devices. Oxidation and diffusion in reactive environment have been carried out with TSUPREM4 [Tec95].

Figure 9.2 shows the resulting net doping concentration in both the N and P devices. Despite the interaction of fundamentally different simulation tools and the large number of simulation steps, fully automatic simulation has been performed without the necessity for user interaction at any point of the simulation. Figure 9.3 shows a detail of the resulting triangular grid after the last process step. 13000 grid nodes are used to accurately resolve arsenic, boron, and phosphorus distributions generated by PROMIS, PROMIS-NT, and TSUPREM4. All grid operations, from the generation of the initial grid to merging and updating grid data at various points in the process flow, have been carried out by the TRIANGLE [She96] gridding tool. Using the framework's built-in dynamic load balancing mechanism on a DEC 3000-600 workstation cluster, the total computation time for all process simulation and regrid operations amounts to less than 17 hours of real time.

 table2502
Table 9.1:   CMOS process sequence. 55 simulation tool steps are used to simulate the entire fabrication process.

 figure2559
Figure 9.2:   Net doping distribution in CMOS inverter after simulation of second metal layer. The N-device on the left side uses an LDD structure and an anti-punch-through implant.

 figure2568
Figure 9.3:   Grid detail of N-device spacer region with LDD implant, source/drain implant, channel implant, and anti-punch-trough implant after simulation of metal 2.


next up previous index
Next: 9.2 Short Channel Effect Up: 9 Application Examples Previous: 9 Application Examples

Christoph Pichler
Thu Mar 13 14:30:47 MET 1997