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5.3 Device Optimization

The gate-delay time with respect to the $ \ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio can be used to compare devices with different geometries and material properties [263]. The gate-delay time is defined next and it is approximated for CNT-FETs. Then we show that by appropriate selection of the spacer lengths the gate-delay time with respect to the $ \ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio can be well optimized.
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M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors