4.1.1.3 Contributions to ${\it C}_{\mathrm{ds}}$

The drain source capacitance ${\it C}_{\mathrm{ds}}$ originates from the capacitive coupling of the source and drain and represents the intrinsic output capacitance in the standard model of Fig. 4.1. Bias dependent contributions to ${\it C}_{\mathrm{ds}}$ arise from buffer and channel layers depending on the channel carrier distribution. Since a one-dimensional model does not consider a ${\it V}_{\mathrm{DS}}$ voltage, the analysis remains for a two- or three-dimensional model. ${\it C}_{\mathrm{ds}}$ can be written as:

$${\it C}_{\mathrm{ds}} ({\it V}_{\mathrm{DS}}) = \sum {\it C}_{\mathrm{ds}}^j$$ (4.6)

where the index j represents all layers between gate metal and semi-insulating substrate in Fig. 3.1. Thus, the elements ${\mit g}_{\mathrm{m}}$, ${\it C}_{\mathrm{gs}}$, ${\it C}_{\mathrm{gd}}$, and even ${\it C}_{\mathrm{ds}}$ find a relatively neat physical interpretation in compact models. For the other four elements a physical interpretation can be found, but unfortunately the non-ambiguous transformation of eight S-parameters into eight small-signal elements leads to rather abstract quantities for their physical interpretation.