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2.3 Gate voltage dependence

We start by analyzing the dependence of the subthreshold voltage on the starting gate voltage (low-level) of the sweep from accumulation to inversion (up-sweep, \( \uparrow \)). Fig. 2.2 shows the drain current (math image) during a gate voltage sweep starting at varying negative gate bias to \( \ac {vg}=\SI {4}{\V } \) (up-sweep, blue) and from \( \ac {vg}=\SI {4}{\V } \) back to varying negative bias (down-sweep, red) at a drain voltage \( V_\textrm {D} \) of 0.1 V. The measurement pattern is sketched in the inset of Fig. 2.2: the down-sweep was performed with a slope of \( \SI {-1}{\V }/\SI {100}{\milli \s } \) right after the up-sweep with a slope of \( \SI {0.1}{\V }/\SI {100}{\milli \s } \). While monitoring the gate voltage level at which \( \ac {id}=\SI {1}{\nano \ampere } \), \( \ac {Vsth}(\uparrow ) \), we observe a shift of \( \ac {Vsth}(\uparrow ) \) to more negative gate voltages the more negative the up-sweep starting voltage.

Figure 2.2: Increase of the sweep hysteresis depending on the starting voltage of the up-sweep from accumulation to inversion (blue). The inset shows the measurement procedure which consists of gate voltage sweeps with varying low level but constant high level. The down sweep from inversion to accumulation is indicated in red. Drain voltage was set to 100 mV.

So far, the effect is consistent with negative bias temperature instability (NBTI), which occurs on all MOS technologies, meaning a negative gate stress results in a negative shift of the threshold voltage. However, there are multiple deviations from the typical NBTI behavior regarding the observed hysteresis effect. One of which is the dependence of the subthreshold voltage shift (math image) on the up-sweep starting voltage as shown in Fig. 2.3. As long as the up-sweep starting voltage is higher or equal to −3 V, no (math image) is observed. Decreasing the up-sweep starting voltage below −3 V leads to a growth of the hysteresis. From this point on, (math image) grows linearly with decreasing up-sweep starting voltage until it saturates for gate voltages \( \ac {vg}\le \SI {-12}{\V } \), meaning any further decrease of the gate voltage does not lead to an increase in (math image). Furthermore, the hysteresis is independent of the high level of the gate pulse as long as it is above the threshold voltage (math image). From the maximum (math image) of approximately −4.5 V and (1.8), we extract a density of trapped charges of \( \ac {Nt} \approx \SI {1.5e12}{\per \centi \meter \squared } \) assuming all charges are captured at the SiC/SiO2 interface.

Figure 2.3: Subthreshold voltage shift extracted from the data in Fig. 2.2 at a drain current of 1 nA (dotted line) as a function of the up-sweep starting voltage. The hysteresis starts to increase linearly with decreasing up-sweep starting voltage as soon as it falls below −3 V and saturates for up-sweep starting voltages below −15 V, where accumulation is reached (see Fig. 2.4). Decreasing the up-sweep starting voltage below −15 V does not lead to any significant increase in the hysteresis.

Figure 2.4: Normalized capacitance voltage CV curve (red) with a inset of the subthreshold voltage shift (blue) as given in Fig. 2.3. The hysteresis starts to grow, as soon as the up-sweep starting voltage falls below \( \ac {vg} < \SI {-3}{\V } \) and holes become avail- able at the interface. Furthermore, the hysteresis saturates as soon as the system approaches strong accumulation, which is the case for gate voltages below \( \ac {vg} = \SI {-15}{\volt } \).

The mechanism behind the hysteresis growth becomes more clear by analyzing the CV curves. Fig. 2.4 shows a schematic CV curve (red) with an inset of the hysteresis curve (blue). The hysteresis in the up-sweep emerges as soon as the starting voltage falls below the intrinsic Fermi level (math image) (in this case \( \ac {vg} \le \SI {-3}{\V } \)). As a consequence of the further decreasing gate voltage, the density of holes at the SiC/SiO2 interface becomes larger than the density of electrons at the interface allowing for hole capture in interface and/or border traps. The process becomes increasingly more efficient until strong accumulation is reached at approximately −15 V and the hysteresis saturates. The explanation of the observed hysteresis by hole capture is consistent with the sign of the threshold voltage shift: a positive charge captured at the interface acts like an additional positive gate potential resulting in a negative threshold voltage shift.

2.3.1 The difference to silicon based devices

There are two reasons why the hysteresis is a feature only observed on SiC based MOSFETs:

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