List of Figures

• 2.1 Part of a cross-sectioned device and the simplified geometry used for simualtion.
• 2.2 A beam of high energy primary electrons generates secondary electron-hole pairs by impact ionization.
• 2.3 Band bending in a nonuniformly doped semiconductor.
• 2.4 The injected electrons and the electron-hole pairs generated by impact ionization cause an additional change in the surface potential in the vicinity of the injection position.
• 2.5 Doping concentration of a p⁺n diode with N _A0 = 10¹⁶ cm^-3, N_D = 10¹⁴ cm^-3, and d= 10^-8 cm.
• 2.6 Electric field in the space charge region.
• 2.7 Potential in the space charge region.
• 2.8 Band structure at the surface of the semiconductor.
• 2.9 Doping distribution of the simulated p⁺n diode. The metallurgical junction is located at x = 0.4 ^. 10^-6 m.
• 2.10 Geometry of the simulated test devices.
• 2.11 AVC potential of a p⁺n diode.
• 2.12 Second derivative of the AVC potential of a p⁺n diode. The metallurgical junction is located at x = 0.4 $\mu$m.
• 2.13 Shift of the location where the second derivative of the AVC potential of a p⁺n diode equals zero as function of the electron beam current.
• 2.14 AVC potential of a n⁺p diode.
• 2.15 Second derivative of the AVC potential of a n⁺p diode. The metallurgical junction is located at x = 0.4 $\mu$m.
• 2.16 Shift of the location where the second derivative of the AVC potential of a n⁺p diode equals zero as function of the electron beam current.
• 2.17 Secondary electrons and holes diffuse away from the injection location. When the minority carriers reach the space charge region they are pulled across the junction by the built-in electric field.
• 3.1 Material types and partitioning of the simulation domain into segments for a simplified HEMT.
• 3.2 Rapid variation of a continuous band edge at the interface x₀.
• 3.3 Idealized discontinuous band edge model.
• 3.4 Model of discontinuous band edge using three distinct values.
• 3.5 Model server, model classes, and derived model classes.
• 3.6 Finite box discretization.
• 3.7 The conduction band edge at the interface for (a) thermionic emission and (b) thermionic field emission.
• 3.8 One-dimensional discretization of the continuity equation across an interface. The boundary values n₁ and n₄ are fixed (Dirichlet boundary condition). For the current across the interface the thermionic field-emission model (3.12) is used.
• 3.9 Schematic cross section of the simulated delta-doped pseudomorphic double-heterojunction HEMT.
• 3.10 Electron concentration along a vertical cut across the channel of a pseudomorphic HEMT.
• 3.11 Electron temperature along the same vertical cut as in Fig. 3.10.
• 3.12 Electron concentration in the channel below the gate.
• 3.13 Electron temperature in the channel below the gate.
• 4.1 Schematic cross section of two cells of a three-phase, n-channel CCD and electron energy at the semiconductor-oxide interface for different applied clock voltages.
• 4.2 Energy band structure for a surface-channel CCD. A potential well forms at the semiconductor-oxide interface.
• 4.3 Energy band structure for a buried-channel CCD. A potential well forms below the semiconductor-oxide interface in the n-type silicon.
• 4.4 Control flow of a transient simulation.
• 4.5 Estimation of the discretization error with the two level step doubling method.
• 4.6 Quadratic step size prediction.
• 4.7 To accurately follow the predefined input signal the step size has to be reduced to match the instance t_k.
• 4.8 When the double estimated step size is greater than the difference between the next instance t_k and the current time t_n the step size has to be reduced to avoid strong step size variations.
• 4.9 Quadratic step size prediction.
• 4.10 Extrapolation of additional points for non-differentiable input signals.
• 4.11 Geometry of the simulated three-phase, n-channel SCCD.
• 4.12 Clock voltages during the first two clock periods.
• 4.13 Electron concentration in the channel region at t = 17.47 ^. 10^-6 s.
• 4.14 Electron concentration in the channel region at t = 17.54 ^. 10^-6 s.
• 4.15 Charge transferred through the source, drain, and bulk contact of the simulated CCD during 10 clock periods. Current flowing into the device is counted positive.
• 5.1 Geometry of the original VDMOS.
• 5.2 Geometry used for simulation.
• 5.3 Source-drain resistance of the conventional device.
• 5.4 Maximum electric field of the conventional device.
• 5.5 Modified device structure with increased doping concentration in the n-epi-layer and an additional vertical p-doped area.
• 5.6 Modified device structure with vertical n- and p-doped areas underneath the gate contact.
• 5.7 Modified device structure with two vertical n- and p-doped areas.
• 5.8 Concentration of the phosphorus doping of the modified device.
• 5.9 Concentration of the boron doping of the modified device.
• 5.10 On-resistance of the optimized device.
• 5.11 Maximum electric field of the optimized device.
• 5.12 On-resistance for variations of the epi layer thickness.
• 5.13 Maximum electric field for variations of the epi layer thickness.
• 5.14 On-resistance for variations of the n-doping width.
• 5.15 Maximum electric field for variations of the n-doping width.
• 6.1 Geometry of the simulated BJT.
• 6.2 log(I_c) and log(I_B) vs. V_be.
• 6.3 Simulated log(I_c) and log(I_b) vs. V_be.
• 6.4 Forward current gain.
• 6.5 Simulated log(I_e) and log(I_b) vs. V_bc.
• 6.6 Reverse current gain.
• 6.7 Output characteristic for different base-emitter voltages.
• 6.8 Control flow of the optimization of the extracted model parameters.
• 6.9 Comparison of log(I_c) and log(I_b) vs. V_be simulated by MINIMOS-NT and SPICE.
• 6.10 Comparison of log(I_e) and log(I_b) vs. V_bc simulated by MINIMOS-NT and SPICE.
• 6.11 Comparison of log(I_e) and log(I_b) vs. V_bc simulated by MINIMOS-NT and SPICE for V_bc = 0.3 - 0.9 V.
• 6.12 Comparison of log(I_e) and log(I_b) vs. V_bc simulated by MINIMOS-NT and SPICE for V_bc = 0.9 - 1.4 V.
• 6.13 Comparison of the output characteristic simulated by MINIMOS-NT and SPICE.
• 6.14 HF circuit diagram of a Colpitts oscillator.
• 6.15 Circuit diagram of the simulated Colpitts oscillator.
• 6.16 Oscillator output voltage simulated by MINIMOS-NT.
• 6.17 Oscillation frequency simulated by MINIMOS-NT.
• 6.18 Base-emitter voltage simulated by MINIMOS-NT.
• 6.19 Collector-emitter voltage simulated by MINIMOS-NT.
• 6.20 Oscillator output voltage simulated by SPICE.
• 6.21 Oscillation frequency simulated by SPICE.
• C.1 Equivalent circuit of the Gummel-Poon model.