Eigene Veröffentlichungen

[V1]

P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr, ``Grid generation for three dimensional process and device simulation,'' in Simulation of Semiconductor Processes and Devices, (Tokyo, Japan), pp. 161-166, Business Center for Academic Societies Japan, 1996, (eingeladen).

[V2]

A. Stach, R. Sabelka, and S. Selberherr, ``Three-dimensional layout-based thermal and capacitive simulation of interconnect structures,'' in Proc. 16th IASTED Int. Conf. on Modelling, Identification and Control, (Innsbruck), pp. 16-19, 1997.

[V3]

R. Sabelka, K. Koyama, and S. Selberherr, ``STAP--A finite element simulator for three-dimensional thermal analysis of interconnect structures,'' in Simulation in Industry--9th European Simulation Symposium, (Passau, Deutschland), pp. 621-625, Okt. 1997.

[V4]

R. Sabelka and S. Selberherr, ``SAP--A program package for three-dimensional interconnect simulation,'' in Proc. Intl. Interconnect Technology Conference, (Burlingame, USA), pp. 250-252, June 1998.

[V5]

R. Martins, W. Pyka, R. Sabelka, and S. Selberherr, ``High-precision interconnect analysis,'' IEEE Trans.Computer-Aided Design, vol. 17, no. 11, pp. 1148-1159, 1998.

[V6]

R. Martins, W. Pyka, R. Sabelka, and S. Selberherr, ``Modeling integrated circuit interconnections,'' in Proc. Int. Conf. on Microelectronics and Packaging, (Curitiba, Brasilien), pp. 144-151, Aug. 1998.

[V7]

R. Martins, R. Sabelka, W. Pyka, and S. Selberherr, ``Rigorous capacitance simulation of DRAM cells,'' in Simulation of Semiconductor Processes and Devices (K. D. Meyer and S. Biesemans, eds.), pp. 69-72, (Leuven, Belgien), Sept. 1998.

[V8]

R. Sabelka, R. Martins, and S. Selberherr, ``Accurate layout-based interconnect analysis,'' in Simulation of Semiconductor Processes and Devices (K. De Meyer and S. Biesemans, eds.), pp. 336-339, (Leuven, Belgien), Sept. 1998.

[V9]

C. Harlander, R. Sabelka, R. Minixhofer, and S. Selberherr, ``Three-dimensional transient electro-thermal simulation,'' in 5th THERMINIC Workshop, (Rome, Italy), pp. 169-172, Okt. 1999.

[V10]

C. Harlander, R. Sabelka, and S. Selberherr, ``Inductance calculation in interconnect structures,'' in Proc. 3rd Int. Conf. on Modeling and Simulation of Microsystems, pp. 416-419, (San Diego, USA), März 2000.

[V11]

R. Sabelka, Ch. Harlander, and S. Selberherr, ``Propagation of RF signals in microelectronic structures,'' in Abstracts Challenges in Predictive Process Simulation, pp. 50-51, (Wandlitz, Deutschland), Mai 2000, (eingeladen).

[V12]

R. Sabelka, Ch. Harlander, and S. Selberherr, ``The state of the art in interconnect simulation,'' in Simulation of Semiconductor Processes and Devices, pp. 6-11, (Seattle, USA), Sep. 2000, (eingeladen).

[V13]

R. Sabelka, and S. Selberherr, ``A finite element simulator for three-dimensional analysis of interconnect structures,'' Microelectronics Journal, vol. 32, no. 2, pp. 163-171, 2001.