D I S S E R T A T I O N

Ultra-Low-Power CMOS Technology

ausgeführt zum Zwecke der Erlangung des akademischen Grades
eines Doktors der technischen Wissenschaften

eingereicht an der Technischen Universität Wien
Fakultät für Elektrotechnik

von

Gerhard Schrom

Adamsgasse 3/3
A-1030 Wien
Matrikelnummer 8326270
geboren am 3.September 1963 in Wien

Wien, im Juni 1998

• Kurzfassung
• Abstract
• Acknowledgment
• Contents
• 1. Introduction
  • 1.1 Supply Voltage, Reliability, and Power Consumption
  • 1.2 Ultra-Low-Power CMOS
  • 1.3 The Role of TCAD for Technology Development
  • 1.4 Outline of this Thesis
  • 1.5 Typographic and Notational Conventions
• 2. The Ultra-Low-Power Approach
  • 2.1 Digital-Circuit Speed and Power Consumption
  • 2.2 Characteristic Voltages
    • 2.2.1 Tradeoff Between Speed and Power Efficiency
  • 2.3 The Role of Leakage
    • 2.3.1 Subthreshold Leakage
    • 2.3.2 Other Types of Leakage
    • 2.3.3 Threshold Design
  • 2.4 Absolute Lower Bounds
    • 2.4.1 Lower Bound of the Supply Voltage
    • 2.4.2 Lower Bound of the Switching Energy
  • 2.5 Achievable Lower Bounds in Static and Dynamic Logic
  • 2.6 Circuit Technique
  • 2.7 ULP Process Technology
    • 2.7.1 Basic Process
    • 2.7.2 Threshold Control
  • 2.8 Power Supply Issues
    • 2.8.1 Batteries
    • 2.8.2 Solar Cells
    • 2.8.3 Voltage Converters
  • 2.9 ULP Leverage
• 3. VLSI Performance Estimation
  • 3.1 Delay Time
    • 3.1.1 Determining Delay Time
    • 3.1.2 Interconnect Delay
    • 3.1.3 Device Delay
    • 3.1.4 Inverter Delay
    • 3.1.5 Gate Delay
    • 3.1.6 Clock Frequency
  • 3.2 Power Consumption
    • 3.2.1 Origins of Power Consumption
    • 3.2.2 Logic Style
      • 3.2.2.1 Standby Mode
    • 3.2.3 Parallel Systems and Pipelining
  • 3.3 VLSI Performance Metric Based on Minimum TCAD Simulations
    • 3.3.1 Introduction
    • 3.3.2 System Model
    • 3.3.3 Device Simulation
    • 3.3.4 Key Parameters and Informational Parameters
    • 3.3.5 Dynamic Inverter Model
    • 3.3.6 Power Consumption
    • 3.3.7 Noise Margins, Inverter Gain, and Output Swing
    • 3.3.8 Application
• 4. Device Modeling for ULP Circuit Simulation
  • 4.1 Why Bother with Device Models?
  • 4.2 Basic Requirements and Types of Models
    • 4.2.1 Accuracy and Consistency
    • 4.2.2 Parametric and Non-Parametric Models
  • 4.3 A Table-Based Device Model for ULP Applications
    • 4.3.1 Introduction
    • 4.3.2 Transient Device Characterization
    • 4.3.3 Model Function and Simulation Environment
    • 4.3.4 Applications
• 5. ULP-Compatible Mixed Analog Circuits
  • 5.1 Operational Amplifiers
  • 5.2 Switched-Capacitor Circuits
    • 5.2.1 Analog Switches
    • 5.2.2 Switched-Capacitor Resistors
  • 5.3 Low-Voltage Analog Digital Conversion
    • 5.3.1 First-Order Sigma-Delta Converters
    • 5.3.2 Second-Order Sigma-Delta Converters
    • 5.3.3 DACs
• 6. Constrained Optimization of Deep-Sub-Micron Devices
  • 6.1 Device Structure Definition and Simulation
  • 6.2 Design of Experiments
  • 6.3 Evaluation and Optimization
  • 6.4 Optimization Criteria and Results
  • 6.5 Summary
• 7. Summary and Outlook
• A. VLSI Technology
  • A.1 MOS Transistors
    • A.1.1 The Field Effect Transistor
    • A.1.2 The Concrete MOSFET (I): Long-Channel Transistors
      • A.1.2.1 Strong Inversion
      • A.1.2.2 Subthreshold Current
      • A.1.2.3 Moderate Inversion
      • A.1.2.4 Speed and Scaling
    • A.1.3 The Concrete MOSFET (II): Sub-Micron Transistors
      • A.1.3.1 Sub-Micron MOSFET Structures and Technology Scaling
      • A.1.3.2 Spurious Effects in Sub-Micron MOSFETs
  • A.2 Digital Circuits
    • A.2.1 MOS Transistor Switches and Boolean Values
    • A.2.2 Basic Circuits and Boolean Algebra
      • A.2.2.1 CMOS Inverters
      • A.2.2.2 Logic Blocks
      • A.2.2.3 Transmission Gates, Tri-State Inverters, and Buffers
      • A.2.2.4 Storage Elements: Latches and Registers
    • A.2.3 Types of Logic Circuits
      • A.2.3.1 Static CMOS Logic
      • A.2.3.2 Dynamic CMOS Logic
      • A.2.3.3 Pseudo-NMOS Logic
      • A.2.3.4 Cascade Voltage Switch Logic
      • A.2.3.5 Pass Transistor Logic
  • A.3 Digital Systems
    • A.3.1 System Modeling
    • A.3.2 Parallel Systems and Pipelining
  • A.4 CMOS Process Technology
    • A.4.1 CMOS Building Blocks
    • A.4.2 An Advanced CMOS Process
  • A.5 Other IC Technologies
    • A.5.1 SOI
    • A.5.2 Bipolar and BiCMOS
    • A.5.3 GaAs
• B. Sigma Delta Converters
  • B.1 First and Second-Order Noise Shaping Loops
  • B.2 Noise and Distortion Analysis
    • B.2.1 First-Order Loop
      • B.2.1.1 Finite Integrator Gain
      • B.2.1.2 Overdrive
    • B.2.2 Second-Order Loop
      • B.2.2.1 Spurious Effects in the Second-Order Loop
  • B.3 Prediction
• C. Off-Current Scaling
  • C.1 Automatic Adjustment of the Channel Doping
• D. Energy Recovery
  • D.1 Diabatic and Adiabatic Switching
  • D.2 Adiabatic CMOS
  • D.3 Scalability of adiabatic CMOS
  • D.4 Simple Adiabatic Techniques
• E. Threshold Voltage - A Critical Review
  • E.1 Definitions
  • E.2 Discussion
  • E.3 Numerical Results
  • E.4 Summary
• Bibliography
• About this document ...