A.3.2 Parallel Systems and Pipelining

Parallelization is a method to increase a system's performance or to achieve the required performance with a slower technology, e.g., with a ULP technology. Figure A.17 shows a simplified parallel system with a three-fold throughput for a given clock frequency at the expense of a more than three times larger chip area. Another approach is pipelining, which means essentially a reduction of the logic depth so that the clock frequency can be increased as shown in Fig. A.18.

Figure A.17: Parallel system

Figure A.18: Pipelined system

In both cases a certain additional overhead such as multiplexing and demultiplexing of data must be paid for the implementation of parallel and pipelined systems [12,58,5].