A.4.2 An Advanced CMOS Process

Figures A.20-A.30 show the process sequence and intermediate results of an advanced CMOS process with twin wells (i.e., both n and p wells are implanted), shallow trench isolation, halo implants (to control short-channel effects), and salicided (i.e., self-aligned silicide formation) gate poly (i.e., polysilicon) and source/drain diffusion zones. Such a process would be typically used for high-performance digital applications with a gate length of $\ensuremath{L}\xspace \le \rm0.25\mu m$. The number of metalization levels could be 5-7 in this case, however, the flow stops after the first level of metalization for simplicity. A legend of the materials is given in Fig. A.19, which applies also to all other cross-sectional figures in this thesis.

Figure A.19: Legend of materials

Figure A.20: Starting material: p-type substrate with a thin epitaxial layer

Figure A.21: N-well and p-well high-energy implants and anneal

Figure A.22: Isolation-trench etch and channel-stop implants

Figure A.23: Trench fill, etch-back, and threshold adjust implants

Figure A.24: Gate oxidation, gate poly deposition, and gate poly etch

Figure A.25: Shallow source/drain extension implants and tilted halo implants

Figure A.26: Sidewall spacer formation

Figure A.27: Deep source/drain implants

Figure A.28: Salicidation

Figure A.29: First intermetal oxide deposition

Figure A.30: Contact hole etch, contact hole fill, metal1 deposition, and metal1 etch