The idea of the silicon-on-insulator (SOI) technology is to replace
the semiconductor below the channel region of a MOSFET with an insulator
so as to eliminate or reduce the effects of the parasitic components.
The resulting device contains only a thin film of semiconductor, which
is partially or fully depleted underneath the gate.
For fully depleted SOI this results in a number of advantages:
the effects of the depletion capacitance per area
and of the source and drain junctions are
mostly
eliminated, which results in an ideal subthreshold behavior
(i.e.
), greatly reduced junction
capacitances
,
and immunity against punch-through and alpha
particles. Especially the good subthreshold behavior makes SOI
attractive for low-voltage applications.
There are, however, some severe drawbacks of SOI, which have their
origins in economics and circuit issues rather than in mere device
physics: the cost for SOI wafers is much higher than for conventional
bulk-technology wafers, the advantages of almost-zero junction
capacitance cannot be fully exploited in a circuit because drains are
always connected to other gates via interconnects and
because of potential circuit instability.
Finally, short-channel effects are
somewhat reduced but not eliminated. This also limits the maximum
allowable thickness of the substrate insulator, which results in a
tradeoff between
roll-off and DIBL on the one hand and
subthreshold slope and drain capacitance on the other.
Thus, despite the remaining advantages of SOI, this technology is not a silver bullet against the spurious effects of bulk technology, all the more as many options of bulk technology have not been exploited yet. This has so far held back a transition to SOI for high-volume high-performance digital VLSI applications. In other fields such as smart-power technologies SOI is a well-established niche technology due to its excellent isolation properties and the integrability with high-voltage and high-power devices. This provides for an ongoing improvement of SOI wafer fabrication and keeps the SOI question for digital VLSI open.