3.1.4 Inverter Delay

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3.1.4 Inverter Delay

The delay time of an unloaded inverter $\ensuremath{t_{\mathit{i,0}}}$ is generally greater than twice the transistor delay of the NMOS transistor due to the lower drive current $\ensuremath{I_{\mathit{on,p}}}$ of the PMOS transistor:

$\begin{displaymath} \ensuremath{t_{\mathit{i,0}}}\xspace \approx \frac{1}{2} ... ...mathit{tr,n}}}\xspace \ensuremath{C_{\mathit{tr,n}}}\xspace . \end{displaymath}$

(3.7)

When the inverter is loaded with an additional capacitance (usually interconnects or gate inputs) the delay time is increased accordingly. Note, however, that delay times in a real circuit are also waveform dependent and the influence of additional capacitive loading is not strictly linear. An accurate model for the inverter delay is developed in Section 3.3.5, where three fit parameters are introduced to enable the calibration of the delay time model.

G. Schrom