3.3.7 Noise Margins, Inverter Gain, and Output Swing

The determination of the static noise margins (cf. Section A.2.2.1) $\ensuremath{{\mathit{NM}}_{\mathit{H}}}\xspace$, $\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace$ would require circuit simulation of an inverter. A close estimate of the noise margins can be determined from just two DC simulations (4a, 4b). Exploiting the fact that the input voltages $\ensuremath{V_{\mathit{IH}}}\xspace$, $\ensuremath{V_{\mathit{IL}}}\xspace$ will be around $\ensuremath{V_{\mathit{DD}}/2}\xspace$ and that one of the output transistors is in saturation, the following algorithm can be used to determine the noise margins: The currents and conductances at the critical voltages (i.e., where the inverter gain is $\vert\ensuremath{A_{\mathit{inv}}}\xspace \vert=1$) are estimated by scaling two IV curves according to Fig. 3.7. With $I_1(V) = \ensuremath{I_{\mathit{D}}}\xspace (\ensuremath{V_{\mathit{G}}}\xspace =V,\ensuremath{V_{\mathit{D}}}\xspace =\ensuremath{V_{\mathit{DD}}/2}\xspace )$, $I_2(V) = \ensuremath{I_{\mathit{D}}}\xspace (\ensuremath{V_{\mathit{D}}}\xspace =V,\ensuremath{V_{\mathit{G}}}\xspace =\ensuremath{V_{\mathit{DD}}/2}\xspace )$, and $\ensuremath{I_{\mathit{sc}}}\xspace = I_1(\ensuremath{V_{\mathit{DD}}/2}\xspace ) = I_2(\ensuremath{V_{\mathit{DD}}/2}\xspace )$ the critical voltages $\ensuremath{V_{\mathit{IL}}}\xspace$, $\ensuremath{V_{\mathit{OH}}}\xspace$ can be obtained by solving:

$$\renewcommand {1.20}{1.6} \begin{array}{rcl} I_1(\ensure... ...xspace )}{\ensuremath{I_{\mathit{sc}}}\xspace }} \end{array}$$ (3.27)

The input-low noise margin $\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace$ is then

$$\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace = \frac{\ens... ...{\mathit{OH}}}\xspace )}{\ensuremath{V_{\mathit{DD}}}\xspace }$$ (3.28)

and the input-high noise margin is determined accordingly (cf. (A.18)). In the case of a single-device analysis the inverter transfer curves are symmetric and the noise margins are $\ensuremath{{\mathit{NM}}_{\mathit{L}}}\xspace = \ensuremath{{\mathit{NM}}_{\mathit{H}}}\xspace = \ensuremath{{\mathit{NM}}}\xspace$. The noise margins of gates can be estimated also by scaling the currents I₁, I₂ according to the fan-in and the logic style, e.g., for a static-logic NAND gate with a fan-in of $\ensuremath{F_{\mathit{in}}}\xspace$ we obtain $\tilde{I}_1 = I_1/\ensuremath{F_{\mathit{in}}}\xspace , \, \tilde{I}_2 = I_2\!\cdot\!\ensuremath{F_{\mathit{in}}}\xspace$. Inverter gain and output voltage swing are determined as $\ensuremath{A_{\mathit{inv}}}\xspace = \ensuremath{g_{\mathit{m}}}\xspace /\ens... ...e =\ensuremath{V_{\mathit{D}}}\xspace =\ensuremath{V_{\mathit{DD}}/2}\xspace }$   and $\ensuremath{{\mathit{OS}}}\xspace = ({\ensuremath{V_{\mathit{DD}}}\xspace - 2 \... ...ce \ensuremath{R_{\mathit{on}}}\xspace })/\ensuremath{V_{\mathit{DD}}}\xspace$   from 4a/4b and 2/5a respectively.

Figure 3.7: Determination of static noise margins