Subsections

• 9.1 Motivation
• 9.2 The Semiconductor Equations
• 9.3 Main Steps of the Grid Generation
• 9.4 Construction of a Device Using the Level Set Method
• 9.5 Grid Generation for a TMOSFET
  • 9.5.1 Grid Generation
  • 9.5.2 Device Simulation
  
  
• 9.6 Grid Generation for an SOI Power Device
  • 9.6.1 Grid Generation
  • 9.6.2 Results and Discussion of Device Simulation
  
  
• 9.7 Summary

9. Application of ELSA to Mesh Generation

In this chapter we present the application of ELSA to an area which is not especially considered in the literature. It is the use of the level set method for the generation of structurally aligned grids. The grids are generated using ELSA based on the technique proposed in [80]. However, the grid generation is performed by a few extensions.

Examples of a trench gate MOSFET and an RF (radio frequency) SOI (silicon-on-insulator) LDMOS (laterally diffused MOS) power device using the device simulator are presented to show how practicable this method is. The device simulations are performed on a grid generated by this new algorithm. In order to accurately resolve the interesting regions of the above mentioned devices, several areas of refinement were defined where the grid was constructed based on varying resolutions.

9.1 Motivation

The quality of a mesh plays a very important role for the numeric solution of semiconductor device equations using a finite element or finite difference method. Because of this quality dependence on the underlying mesh, structurally aligned grids are a crucial prerequisite for accurate device simulation, which needs to solve partial differential equation. In addition, for aligning the meshes within the structures, it is also desirable to enforce quality criteria like the Delaunay criterion or the minimum angle criterion [33].

We present a new method to generate structurally aligned grids with optional anisotropy. The basic idea is using a level set algorithm for advancing a front through the simulation domain. This leads to construct a suitable set of edges for the next steps of the mesh generation. After extracting and reworking the boundaries these edges are used in a second step as the input to a specialized grid generator that enforces the specified quality criteria. Although a technique based on the level set method has been used for the generation of structurally aligned grids [77], that method cannot generate anisotropic grids and no condition concerning the quality of the grid, e.g., minimum angles or the Delaunay criterion, can be guaranteed. However, our approach has been successfully applied to semiconductor device simulation. The generated grids were used with the simulator MINIMOS-NT.

9.2 The Semiconductor Equations

The Poisson and the continuity equations for electrons and holes [75,58,5], are the basic equations used for semiconductor device simulations. The default carrier transport model in MINIMOS-NT is the drift-diffusion model which can be derived from the Boltzmann equation by the method of moments.

The main difficulties in the numerical treatment of the drift-diffusion equations are first their nonlinearity and second the large differences among the magnitude of the variables which are involved in these equations. These differences cause an almost singular behavior of the solution of drift-diffusion equations [58]. It is also known that the solutions of the drift-diffusion equations behave variably in different regions of a device. This is referred to the layer structure of the solutions, i.e., they show large gradients [57]. These steep gradients occur locally across $p$-$n$ junctions and in channel regions, e.g., in the narrow regions underneath semiconductor-oxide interfaces. The singular behavior and layer structure of the solution permit to use singular perturbation analysis [58], which is based on locally replacing the basic equations in different subregions of the device by simpler problems. The solutions of these simplified problems have to guarantee all the essential qualitative features of the original solution. These approximations enable to gain insight into the behavior of the solution which can not be obtained normally by the complex original system.

The information about the layer structure of the solutions is vital when generating grids from a priori information. In contrast, grid refinement techniques are of course based on a posteriori information from error estimators. The solutions of the device equations depend on the location of the junctions, the iso-lines and the distribution of the doping, and the operating conditions. Because of the layer behavior in the vicinity of junctions, the grid can be constructed suitably for certain operating conditions based on the extracted iso-lines before attempting a numerical solution.

9.3 Main Steps of the Grid Generation

In order to generate our structurally aligned grids two main steps have to be taken into account. The first one (cf. Section 9.4) is using a level set algorithm to advance one or more fronts with constant speed functions through the simulation domain. The second one is feeding TRIANGLE [91,92] with the edges constructed in the first step to obtain a Delaunay triangulated grid. A Delaunay triangulation of a vertex set is a triangulation of the vertex set with the property that no vertex in this set falls in the interior of the circumcircle (circle that passes through all three vertices) of any triangle in the triangulation. As mentioned previously, the minimum angle criterion is obeyed using a refinement algorithm for quality mesh generation [70]. The TRIANGLE program used in this work, is written in C and computes two-dimensional Delaunay triangulations. TRIANGLE can be fed using two different kinds of input files. The first kind is a .node file [91,92] which only defines the region for the triangulation based on introducing the vertices. Because a parameter to control the quality when using .node files is lacking we have used the second kind of input file accepted by TRIANGLE, namely .poly file [91,92].

9.4 Construction of a Device Using the Level Set Method

In this section the details of the algorithm devised for the generation of edges which are introduced as input into TRIANGLE, are presented [7].

As mentioned in Section 5.2, the level set function must be initialized to the signed distance function. Within the numeric application the level set function is represented by values on grid points. In order to find the coordinates of the current boundary the surface must be extracted from this grid using linear interpolation. One or more fronts is advanced with constant speed functions through the simulation domain. For each moving front a certain number of boundaries are extracted and reworked. The number of these boundaries and the spacing between them can be defined arbitrarily and depend on the number of advancing level set steps and their time steps. Clearly the spacing between the intermediate boundaries obtained by the level set algorithm will later determine the diameters of the triangles of the resulting grid.

Figure 9.1 shows the triangulated simulation domain after introducing the edges obtained by the level set algorithm into TRIANGLE. Because of the different lengths of the segments which are obtained at each boundary extraction, we can clearly see that this triangulation contains triangles which are too small. An enlarged view of this undesirable situation is shown in Figure 9.2.

Figure 9.1: The triangulated grid without using a segment length equalizer.

Figure 9.2: An enlarged part of the mesh structure shown in Figure 9.1.

This problem originates from a boundary extraction algorithm which is implemented in ELSA and considered firstly just for the deposition and etching processes. It uses an interpolation method to find the points of the boundary and represents these as a list of segments with different lengths. Figure 9.3 shows a part of the last five steps of advancing the front at a larger scale to show more clearly the varying lengths of the segments. The segments may become arbitrarily small and are the cause for the finely trinagulated areas. To overcome this problem we need to ensure that all segments of the boundary have about the same lengths as shown in Figure 9.4 [22,18].

We start the algorithm by choosing a certain length $d$ for all segments. In our example we chose the minimum value of the vertical or horizontal distance between the points of our original rectangular grid which is used in the level set step. The first point of the extracted boundary remains without any changes but to locate the other points we have to discern two cases. In one case the distance between the first point and the second point is equal to or greater than $d$. In other case this distance is smaller than $d$.

In the first case the second point of the recalculated boundary is computed fulfilling the two following restrictions: first, the new segment must be along the first segment of the old segment and second, the length of the new segment must be equal to $d$.

In the second case we compute the second point of the new boundary along the next segment of the original boundary and as in the first case fulfilling the length requirement. These steps are iterated until we reach the boundary of the domain.

Figure 9.3: Enlarged view of the last five steps of the advancement of the front. The varying lengths of the segments are clearly visible.

Figure 9.4: Enlarged view of the last five steps of the advancement of the front after equalizing the lengths of the segments. The length of the segments are now approximately the same.

This first part of the grid generation is highly customizable and anisotropy can be introduced here by choosing the spacing between the intermediate boundaries and the distance between the points of the normalized boundary accordingly.

Now the grid segments are normalized by choosing points on the boundary that are equidistant when their distance is measured along the boundary. The normalized intermediate boundaries consist of straight lines which are edges of the final grid to be respected again in the second part of the algorithm which uses TRIANGLE.

This allows to produce meshes with no small angles while using relatively few triangles. Figure 9.5 shows the triangulated grid after using TRIANGLE without the dense triangles. This can be seen more clearly in Figure 9.6 which depicts exactly the same enlarged area of the meshed structure shown in Figure 9.2.

Figure 9.5: The triangulated grid is caused using the segment length equalizer.

Figure 9.6: A part of the above grid on a larger scale.

The benefits of this algorithm can be summarized as follows. The grid resolution is customizable and the areas of higher resolution can be chosen arbitrarily. The grid resolution may vary over several orders of magnitude. The algorithm can deal with arbitrary initial structures and an arbitrary number of starting fronts, defining areas of high resolution. Anisotropy may be introduced by choosing appropriate parameters for the algorithm. At the same time quality criteria like the Delaunay criterion and the requirement that all angles of the triangulation are larger than a certain minimum angle are enforced. It is important to note that the algorithm works reliably, since it is based on edges in contrast to just prescribing sets of points, hence preserving directional information.

In [102] a different approach to grid generating using a level set algorithm is presented. Previous work along these lines includes [61,52]. Compared to grid generation algorithms using iso-lines or iso-surfaces obtained as solutions of a Poisson equation [96], the advantage of this algorithm is its flexibility. This is important, e.g., near the buried layers of SOI devices. The initial boundaries where the advancing fronts start, the prescribed number of intermediate boundaries and their spacing determine the properties of the final grid in a straightforward manner in contrast to the Poisson equation approach.

Figure 9.7: Structure of the TMOSFET. The half cell pitch of the device is $2.5\mathrm{\mu m}$ and its $n$ drift length is about $9.5\mathrm{\mu m}$.

9.5 Grid Generation for a TMOSFET

TMOSFET s are useful for power switching at high voltages [101,90,16,27,28]. Their geometric layout also provides advantages, because their inversion and accumulation channel regions are perpendicular to the wafer surface. Hence they maximize the ratio of cell perimeter to its area, thus increasing packing density. The TMOSFET considered is a $120\mathrm{V}$ trench gate UMOS transistor. The simulated characteristics of the device after its generating using our approach are presented.

The device structure of the trench gate UMOS transistor is shown in Figure 9.7 and its parameters in Table 9.1. Its trench depth is $3 \mathrm{\mu m}$ and its gate oxide thickness is $0.1 \mathrm{\mu m}$. It is designed to achieve a forward blocking voltage of $120\mathrm{V}$.

Table 9.1: The technological and geometrical parameters of the TMOSFET.

Parameter	Value
$n$ drift doping	$1.5 \times 10^{15} \mathrm{cm}^{-3}$
$p$ well doping	$1 \times 10^{17} \mathrm{cm}^{-3}$
$p$ well	$\approx 1.4\mathrm{\mu m}$
$p^+$ buffer	$5 \times 10^{18} \mathrm{cm}^{-3}$
$n^+$ source depth	$\approx0.38\mathrm{\mu m}$
Gate oxide thickness	$0.1 \mathrm{\mu m}$
Trench depth	$3 \mathrm{\mu m}$
$n$ drift length	$\approx 9.5\mathrm{\mu m}$

9.5.1 Grid Generation

For the grid generation we used four boundaries following the three junctions (cf. Figure 9.7) and one in the $p$-region near the gate oxide. First, at the $n^+$-$p$ junction we used three boundaries in each direction of the initial boundary following the junction with a distance of $0.02\mathrm{\mu m}$ between any adjacent boundaries.

At the $p$-$n$ junction we used one boundary above and below the initial boundary and a distance of $0.02\mathrm{\mu m}$. At the $n$-$n^+$ junction in the lower part of the device we constructed two boundaries with a distance of $0.5\mathrm{\mu m}$ going downwards from the initial boundary following the junction. For the last set of prescribed edges we started at the right hand side of the $p$-region and moved to the left constructing three boundaries at a distance of $0.005\mathrm{\mu m}$.

In the second step we used the TRIANGLE program requiring a minimum angle of $25^\circ$ with the prescribed edges as input. The resulting mesh produced and two enlargements thereof are shown in Figure 9.8 and Figure 9.9. The junction areas are resolved very finely as demanded.

Figure 9.8: The grid generated for the TMOSFET device in Figure 9.7. Two enlargements are shown on the right hand side.

Figure 9.9: Enlargement of the grid shown in Figure 9.8.

9.5.2 Device Simulation

The device simulations were performed using MINIMOS-NT. Figure 9.10 shows typical on-state characteristics of the high voltage TMOSFET. The $I$-$V$ curves of the figure show that good saturation currents behavior is obtained by increasing the drain voltage. Transfer characteristics are shown in Figure 9.11 for drain voltages of $V_d = 0.1\mathrm{V}$ and $0.5\mathrm{V}$. From this figure a threshold voltage $V_T$ of $2.5\mathrm{V}$ is obtained. It is important to note that the threshold voltage is independent of the drain voltage.

Figure 9.10: The on-state characteristics of the vertical TMOSFET for gate voltages of $5\mathrm{V}$, $7\mathrm{V}$, and $10\mathrm{V}$.

Figure 9.11: The transfer characteristics of the high voltage TMOSFET for drain voltages of $0.1\mathrm{V}$ and $0.5\mathrm{V}$.

9.6 Grid Generation for an SOI Power Device

The second example is the simulation of an RF SOI LDMOS power transistor. Several regions of refinement had to be chosen and the specific structure of the device and the location of the junctions have been taken into account. SOI is a promising technology for monolithic integration of digital, analog, and RF devices. For RF power applications the reduced capacitance and the low leakage current of SOI devices are highly demanded. The simulation results presented are the two-dimensional device simulation of a 110V RF SOI-LDMOSFET.

Again, the final grid was obtained by TRIANGLE starting from prescribed edges. The minimum required angle was $20^\circ$. The final grid is shown in Figure 9.12 and an enlargement in Figure 9.13. The parameters of the device is described in Table 9.2. It is designed to achieve a forward blocking voltage of 110V with an SOI thickness $t_\mathrm{soi}$ of $1.5\mathrm{\mu m}$ and with a buried oxide thickness $t_\mathrm{ox}$ of $1.0\mathrm{\mu m}$. The doping of the device is given by analytic functions or, more precisely, Gaussian profiles (cf. Table 9.2).

Figure 9.12: The structure of the RF SOI LDMOS power transistor and the generated grid.

Figure 9.13: Enlargement of the drain region (left) from Figure 9.12.

Table 9.2: The technological and geometrical parameters of the RF SOI LDMOS power transistor. The lateral factor of all Gaussian profiles is $0.8$.

Parameter	Value
$n$ drift length	$6\mathrm{\mu m}$
$n$ drift doping (P)	$3 \times 10^{16} \mathrm{cm}^{-3}$
SOI thickness	$1.5\mathrm{\mu m}$
$p$ epi doping (B)	$1 \times 10^{14} \mathrm{cm}^{-3}$
$p+$ buffer doping (B)	$5 \cdot 10^{18} \mathrm{cm}^{-3}$
$p$ body doping (B)	$7 \times 10^{17} \mathrm{cm}^{-3}$
Sub doping (P)	$1 \times 10^{18} \mathrm{cm}^{-3}$
SiO$_2$ layer thickness	$1 \mathrm{\mu m}$

9.6.1 Grid Generation

To generate the grid we used six boundaries following the four junctions (cf. Figure 9.12), one in the channel, and one at the silicon-insulator interface. First, at the $p$-body-$n+$ junction we used one boundary in each direction of the initial boundary following the junction with a distance of $0.1 \mathrm{\mu m}$ between two adjacent boundaries.

Second, at the $n$-drift-$p$-epi junction we used one boundary above and below the initial boundary and a distance of $0.02\mathrm{\mu m}$. Third, at the $n$-buff-$p$-epi junction we constructed one boundary above and below at a distance of $0.02\mathrm{\mu m}$. For the $n+$-$n$-buff junction boundaries, again one boundary above and below at a distance of $0.1 \mathrm{\mu} m$ were used.

In the channel region we started at the interface and moved down constructing four boundaries at a distance of $0.005\mathrm{\mu m}$. For the last prescribed edges we started at the boundary between the silicon and the silicon dioxide layers and moved up and down at a distance of $0.1 \mathrm{\mu} m$.

9.6.2 Results and Discussion of Device Simulation

The optimum drift length and doping concentration are considered by the RESURF (reduced surface field) principle. With the proposed grid generation algorithm mesh structures suitable for device simulation can be obtained along the junctions (parallel to the junction) and at the buried oxide interface. Again the typical on-state characteristics were obtained using MINIMOS-NT and are shown in Figure 9.14. The $I$-$V$ curves imply that good saturation currents behavior is obtained by increasing the drain voltage. Transfer characteristics are shown in Figure 9.15 for drain voltages of $V_d = 0.1\mathrm{V}$ and $0.5\mathrm{V}$. From this figure a threshold voltage $V_T$ of $1\mathrm{V}$ is obtained.

9.7 Summary

A new method to generate structurally aligned grids and guaranteeing quality criteria on the resulting triangulation was presented. It provides a lot of flexibility, since the resolution and anisotropy of the grid is customizable and the diameter of the triangles may vary over several orders of magnitude within one simulation domain. Compared to the approach of using iso-lines or iso-surfaces of solutions of a Poisson equation [96], this method allows to propagate several fronts through the simulation domain and thus to precisely tailor the areas of high resolution in a straightforward manner.

Furthermore the algorithm is robust since the generation of the final triangulation is based on edges that have to be respected (and not on single points). Finally the grids generated satisfy the Delaunay criterion and the minimum angle criterion which ensures high grid quality with respect to its numeric properties.

Two examples demonstrate the method's aplicability even to non-trivial geometries. The on-state and transfer characteristics were calculated using the meshes obtained by this method.

Figure 9.14: The on-state characteristics of the RF SOI LDMOS power transistor for gate voltages of $5\mathrm{V}$, $10\mathrm{V}$, and $15\mathrm{V}$.

Figure 9.15: The transfer characteristics of the RF SOI LDMOS power transistor for drain voltages of $0.1\mathrm{V}$ and $0.5\mathrm{V}$.