6.4.3 Analytical Profiles

The doping peaks in the channel regions of the NMOS and PMOS devices are substituted by Gaussian functions and the two methods to prevent punchthrough, mentioned in Section 4.4.3, are utilized: Method 1 with the background substrate doping as a free optimization parameter, and Method 2 with the background doping fixed at 10$^{15}$ cm$^{-3}$ and an additional Gaussian function under the source well .

The initial devices are fit manually to the results of the two-dimensional approach and, after running the stand-alone procedure explained in Section 6.4.1, the optimization is started. For a detailed description of the optimization parameter setup please refer to Section 4.4.3. It is to note that due to the increased source and drain well lengths the values of the lateral position parameters have been changed as the origin of the x-axis is at the left border of the device.

Fig. 6.17 and Fig. 6.18 show the acceptor and donor doping profiles of the NMOS and PMOS devices, respectively, as the result of the optimization approach using only one Gaussian function (Method 1) for Device Generation A. The results for Device Generation B are shown in Fig. 6.19 and Fig. 6.20.

Fig. 6.21 and Fig. 6.22 show the acceptor and donor doping profiles of the NMOS and PMOS devices, respectively, as the result of the optimization approach using two Gaussian function (Method 2) for Device Generation A. The results for Device Generation B are shown in Fig. 6.23 and Fig. 6.24.

The resulting parameter values are listed in Table 6.1 for Method 1 and Table 6.2 for Method 2.

Table 6.1: Resulting parameters from the gate delay time optimizations using one Gaussian function.

		Device Generation A		Device Generation B
param.	unit	NMOS	PMOS	NMOS	PMOS
$N_{\mathrm{sub}}$	cm$^{-3}$	3.01$\cdot$10$^{16}$	2.33$\cdot$10$^{16}$	6.53$\cdot$10$^{16}$	1.12$\cdot$10$^{17}$
$N$	cm$^{-3}$	1.29$\cdot$10$^{18}$	1.47$\cdot$10$^{18}$	6.24$\cdot$10$^{18}$	6.82$\cdot$10$^{18}$
$x_0$	$\mu$m	0.41336	0.41772	0.16808	0.16573
$y_0$	$\mu$m	0.01665	0.01444	0.00930	0.01069
$\Delta x$	$\mu$m	0.00000	0.00004	0.00790	0.01099
$\sigma_x$	$\mu$m	0.01702	0.01424	0.01338	0.00867
$\sigma_y$	$\mu$m	0.02165	0.02110	0.00471	0.00429

Table 6.2: Resulting parameters from the gate delay time optimizations using two Gaussian functions.

		Generation A		Generation B
param.	unit	NMOS	PMOS	NMOS	PMOS
Peak 1
$N$	cm$^{-3}$	1.35$\cdot$10$^{18}$	1.34$\cdot$10$^{18}$	6.38$\cdot$10$^{18}$	9.16$\cdot$10$^{18}$
$x_0$	$\mu$m	0.41691	0.41709	0.16810	0.16742
$y_0$	$\mu$m	0.01201	0.01197	0.01001	0.00975
$\Delta x$	$\mu$m	0.00011	0.00007	0.00469	0.00299
$\sigma_x$	$\mu$m	0.01695	0.01694	0.00955	0.00794
$\sigma_y$	$\mu$m	0.01999	0.01996	0.00564	0.00400
Peak 2
$N$	cm$^{-3}$	1.12$\cdot$10$^{18}$	1.11$\cdot$10$^{18}$	3.71$\cdot$10$^{18}$	3.78$\cdot$10$^{18}$
$y_0$	$\mu$m	0.05499	0.05496	0.02456	0.02497
$\Delta x$	$\mu$m	0.32699	0.32697	0.13174	0.13306
$\sigma_x$	$\mu$m	0.04001	0.03997	0.01510	0.01533
$\sigma_y$	$\mu$m	0.01496	0.01496	0.00582	0.00614

Figure 6.17: The NMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation A.

Figure 6.18: The PMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation A.

Figure 6.19: The NMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation B.

Figure 6.20: The PMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation B.

Figure 6.21: The NMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation A.

Figure 6.22: The PMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation A.

Figure 6.23: The NMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation B.

Figure 6.24: The PMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation B.