List of Figures

• 1.1 Comparing an RSM to the real target function.
• 2.1 Transfer curves of a 0.25 $\mu$m MOS transistor for different bulk doping levels.
• 2.2 Potential distribution in units (V) of Device $\alpha$ (top) and Device $\beta$ (bottom).
• 2.3 Current density in units (A/cm$^{-2}$) of Device $\alpha$.
• 2.4 Vertical electron concentration in the channel middle for Device $\alpha$ and Device $\beta$.
• 2.5 Advanced methods to prevent punchthrough using (a) delta doping, (b) halo, and (c) pocket implants.
• 2.6 Surface potential of Device $\beta$ for 0.1 V and 1.5 V drain voltages (linear and saturated case).
• 2.7 Transfer curves of Device $\beta$ for 0.1 V and 1.5 V drain voltage (linear and saturated case).
• 2.8 Impact ionization rate in units (s$^{-1}$cm$^{-3}$) of Device $\beta$ in the on-state.
• 2.9 Lateral electric field at the channel surface of Device $\beta$ in the on-state.
• 3.1 The black box evaluator for optimization purposes.
• 3.2 The used device geometry.
• 3.3 The source and drain doping profiles in units (cm$^{-3}$) for Device Generation A (top) and Device Generation B (bottom).
• 3.4 The two-dimensional doping discretization.
• 3.5 The raised-cosine interpolation method.
• 3.6 The two-dimensional Gaussian function.
• 3.7 The optimization loop.
• 3.8 The optimization sequence.
• 3.9 How SIESTA works.
• 3.10 The SIESTA graphical user interface for the queue status.
• 3.11 The SIESTA graphical user interface visualizing the optimization progress.
• 4.1 Definition of the drive current Ion and the drain leakage current Ioff .
• 4.2 The evaluation network for drive current optimizations.
• 4.3 The drive current improvement during the optimization.
• 4.4 The result of the two-dimensional drive current optimization for Device Generation A.
• 4.5 The result of the two-dimensional drive current optimization for Device Generation B.
• 4.6 The relative drive (top) and leakage current (bottom) sensitivities for Device Generation A.
• 4.7 The relative drive (top) and leakage current (bottom) sensitivities for Device Generation B.
• 4.8 The result of the optimization using Gaussian functions for Device Generation A, Method 1.
• 4.9 The result of the optimization using Gaussian functions for Device Generation B, Method 1.
• 4.10 The result of the optimization using Gaussian functions for Device Generation A, Method 2.
• 4.11 The result of the optimization using Gaussian functions for Device Generation B, Method 2.
• 4.12 The drive current optimization results of the purely vertical optimizations for Device Generation A (top) and Device Generation B (bottom).
• 5.1 The transfer curves of the PCD device and the uniformly doped device in the linear (top) and saturated (bottom) regions, Device Generation A.
• 5.2 The transfer curves of the PCD device and the uniformly doped device in the linear (top) and saturated (bottom) regions, Device Generation B.
• 5.3 Drive current versus gate length of a uniformly doped device: (a) two-dimensional device simulation, (b) analytical model with DIBL, (c) analytical model without DIBL.
• 5.4 Optimal gate length of a uniformly doped device: (a)  Vg  = 1.5 V, (b)  Vd  = 0.5 V, (c)  Vg  =  Vd .
• 5.5 Subthreshold characteristics of the PCD device: (a) finite and (b) infinite peak depth.
• 5.6 The PCD device with infinite peak depth.
• 5.7 A long PCD device and its three-transistor equivalent model.
• 5.8 Variation of the lateral doping peak position: (a, b) drive and leakage current from two-dimensional device simulation, (c, d) using the three-transistor model
• 5.9 Results of the qualitative study on the PCD device.
• 5.10 The transfer curves of the various devices used in this study (devices D1 to D5).
• 5.11 The Vth roll-off of the PCD device compared to the uniformly doped device.
• 5.12 The bulk currents of the PCD device in forward and reverse mode compared to the uniformly doped device.
• 5.13 The lateral electric field in the channel of the PCD device in forward and reverse mode compared to the uniformly doped device.
• 5.14 The FIB implantation method to generate the PCD structure.
• 5.15 The LATI method to generate the modified PCD structure.
• 5.16 The optimization result of the symmetric modified PCD device for Device Generation A.
• 5.17 The optimization result of the modified PCD device for Device Generation A.
• 5.18 The optimization result of the overlapping PCD device for Device Generation A.
• 5.19 The optimization result of the source halo device for Device Generation A.
• 6.1 An infinite CMOS inverter chain.
• 6.2 The single stage inverter model.
• 6.3 The evaluation network for gate delay time optimizations.
• 6.4 The time-shift method used to obtain the inverter input V-t curve from the output V-t curve of the previous step.
• 6.5 The optimization sequence for gate delay time optimizations.
• 6.6 The time-step control method for the transient simulation of the inverter stage transition.
• 6.7 The stand-alone procedure to provide a self-consistent initial state for the gate delay time optimizations.
• 6.8 The inverter delay time improvement during optimization.
• 6.9 The result of the two-dimensional gate delay time optimization for the NMOS, Device Generation A.
• 6.10 The result of the two-dimensional gate delay time optimization for the PMOS, Device Generation A.
• 6.11 The result of the two-dimensional gate delay time optimization for the NMOS, Device Generation B.
• 6.12 The result of the two-dimensional gate delay time optimization for the PMOS, Device Generation B.
• 6.13 The gate delay time (top) and leakage current (bottom) sensitivities for the NMOS, Device Generation A.
• 6.14 The gate delay time (top) and leakage current (bottom) sensitivities for the PMOS, Device Generation A.
• 6.15 The gate delay time (top) and leakage current (bottom) sensitivities for the NMOS, Device Generation B.
• 6.16 The gate delay time (top) and leakage current (bottom) sensitivities for the PMOS, Device Generation B.
• 6.17 The NMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation A.
• 6.18 The PMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation A.
• 6.19 The NMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation B.
• 6.20 The PMOS after gate delay optimization using Gaussian functions, Method 1, Device Generation B.
• 6.21 The NMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation A.
• 6.22 The PMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation A.
• 6.23 The NMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation B.
• 6.24 The PMOS after gate delay optimization using Gaussian functions, Method 2, Device Generation B.
• 6.25 The gate delay time optimization results of the purely vertical optimization for the NMOS (top) and PMOS (bottom), Device Generation A.
• 6.26 The gate delay time optimization results of the purely vertical optimization for the NMOS (top) and PMOS (bottom), Device Generation B.
• 6.27 Input (dashed) and output (solid) curves of the two-dimensional optimization results compared to the uniformly doped device for Device Generation A (top) and Device Generation B (bottom).
• 6.28 The small signal inverter model.
• 6.29 The voltage and current conditions of the NMOS transistor during an off-transition.
• 6.30 The five stage ring oscillator with its initial state.
• 6.31 The node voltages of a five stage ring oscillator using uniformly doped devices (top) and devices with optimized doping profiles (bottom) for Device Generation A.
• 6.32 The node voltages of a five stage ring oscillator using uniformly doped devices (top) and devices with optimized doping profiles (bottom) for Device Generation B.
• A.1 The result of the two-dimensional optimization with the drive current as the constraint.