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5. NBTI Reliability Analysis

While most of the miniaturization problems in CMOS technology are more or less related to doping issues, the continued reduction of the gate oxide thickness has necessitated the incorporation of nitrogen into silicon dioxide, which in turn has aggravated NBTI (negative bias temperature instability), especially, since we have entered the 90nm and 65nm technology nodes. As drive currents increase HCI reliability usually gets worse since the drive current directly determines the carriers generated by impact ionization. However, optimization of the drain extension doping profile reduces the electric field at the drain edge significantly. Therefore, the substrate current, which is a quantitative measure for impact ionization, is strongly reduced for advanced CMOS technologies [115]. Since HCI has lost on importance and NBTI is the leading reliability concern for current technology nodes, a detailed analysis of the degradation and relaxation behavior of the NBTI mechanism in a 90nm transistor is presented.

The key device parameters of the p-MOSFET such as threshold voltage and saturation current show a rapid shift under negative bias at an elevated temperature due to the build-up of positive interface charges. Since indirect measuring techniques have to be applied, it is difficult to correlate measurement results to NBTI induced degradation of the gate-dielectric/substrate interface associated with bond breaking and chemical species. While the exact nature of the complex NBTI mechanism is still unknown, it is widely accepted that interface traps are generated by breaking of hydrogen-passivated silicon bonds at the interface and subsequent diffusion of hydrogen [116,117,25]. Charge pumping and gate leakage current measurements revealed that NBTI under moderate oxide fields is purely due to interface traps $ N_{it}$ and the generated oxide traps $ N_{ot}$ can be neglected [118]. The NBTI induced interface charges cause a parameter degradation of the MOSFET firstly due to a reduction in inversion layer holes and secondly due to a mobility degradation by Coulomb scattering. Both the reduced gate overdrive $ (V_{G} \!- \!V_{T})$ and the degraded mobility reduce the saturation current and the transconductance of the transistor.

Jeppson and Svensson studied the process of trap formation at the Si/SiO $ _{\mathrm{2}}$ interface during NBT stress in MOS capacitors in 1977 [119]. They found that the NBTI-driven shift of the threshold voltage in p-MOSFETs depends on the applied gate voltage, temperature, and stress time. It is commonly assumed that the generated interface states are dangling silicon bonds with an energy distribution within the silicon band gap. Holes can occupy these energy states under inversion condition and produce positive interface charges [116]. For advanced CMOS technologies, nitrogen is incorporated in thinner gate oxides mainly to reduce gate leakage current, to avoid boron penetration into the dielectric, and to improve HCI reliability. However, it turned out that silicon dioxide-nitride compositions exhibit a significantly higher NBTI degradation compared to pure silicon dioxide for the same physical oxide thickness and voltage condition [13]. Experimental studies revealed that the thermal activation energy of interface trap generation decreases steadily with increasing nitrogen concentration at the interface [120,121].

Under dynamic operation of the transistor the interface traps which are generated during the on-state are partially annealed in the off-state. Therefore the AC degradation is significantly lower than the DC degradation for any given stress time. The magnitude of the NBTI driven parameter shift over time is significantly reduced for higher frequencies [122] or smaller ``on''duty cycles [123,124]. In this section we analyze mainly the impact of an operation at higher frequencies in the MHz-range at slightly different supply voltages on the AC lifetime of a 90nm transistor. The NBTI transistor level degradation is closely linked to circuit and product level degradation, which will be analyzed for a typical 90nm-based SRAM memory cell in Section 6.4.

5.1 NBTI Experiments for a 90nm CMOS Technology

The investigated p-MOSFET device was fabricated in a 90nm bulk technology with shallow trench isolation (STI). The gate oxide was annealed in an NO $ \mathrm{_x}$ gas ambient and has a physical oxide thickness of 2.4nm and an equivalent oxide thickness (EOT) of 2.05nm. A dual poly-gate CMOS configuration was used on top of the nitrided gate oxide. Source/drain extension implant profiles and halo implants for punchthrough suppression were created by ion implantation processes before a nitride spacer was deposited. The source/drain regions were implanted subsequently followed by a high temperature RTA annealing step to activate the dopants and to eliminate the crystal damage. The backend was completed by employing local interconnect as well as a triple-layer aluminum-metal process.
Figure 5.1: Configuration for NBTI experiments under DC and AC stress (left) and influence of relaxation during long measuring intervals on the slope of $ I_{Dsat}$ shift at a constant gate voltage stress $ V_{G} \! =\! $-1.5V (right).

The sketch on the left hand side of Fig. 5.1 shows the used configuration for NBTI experiments under DC and AC gate voltage stress conditions at a constant temperature of 125$ ^\circ $C. The used amplitude for AC stress is identical to the negative DC voltage during the pulse ``on'' phase and zero Volt during the pulse ``off'' phase. The NBT stress was interrupted at certain times to measure the threshold voltage and drain saturation current. The threshold voltage $ V_T$ was extracted by using a linear extrapolation of $ I_{D}$ - $ V_{G}$ data from the point of maximum transconductance, and the saturation current $ I_{Dsat}$ was determined at $ V_{G} = -1.2\mathrm{V}$ and $ V_{D} = -1.2\mathrm{V}$.

The measuring interval of the tester used for monitoring the key parameters of the MOSFET over the stress time should be kept as short as possible to minimize the influence of relaxation on measurement results. The diagram on the right hand side of Fig. 5.1 illustrates that the $ I_{Dsat}$ parameter shift is significantly reduced by stronger annealing of interface traps for longer relaxation phases. In the long stress time regime the influence of the relatively short measuring intervals plays a secondary role and the results of long and short intervals become comparable. The longer measuring interval lasts ten times longer than the shorter interval of 700ms.

The accomplishment of all presented NBTI measurements in this section were managed by Dr. Puchner at Cypress Semiconductor Corp. in San Jose. Different rectangular gate signals were used in order to analyze the gate voltage, duty cycle, and frequency dependence of the NBTI degradation behavior. Voltages were applied from -1.5V down to -2.7V to the gate of the transistor, frequencies were used in the range from DC to 1MHz, and ``on'' duty cycles in the range of 30% to 70%. The MOSFET parameters $ V_T$ and $ I_{Dsat}$ were monitored for a maximum stress time of $ 2\cdot10^5$s. The experimental data were used to analyze the relationship between the $ I_{Dsat}$ shift and the $ V_T$ shift, to empirically investigate the gate voltage and frequency dependence of NBTI, and finally to calibrate the numerical simulations for the 90nm p-MOSFET device.

5.2 Reaction-Diffusion Model

Although several NBTI models have been developed to explain the physics of interface trap generation based on electrochemical reactions and activation energies, only the reaction-diffusion (R-D) model can explain to some extend the power-law time dependence of the NBTI degradation. Jeppson and Svensson developed the first model approach in 1977 [119], Ogawa and Shiono generalized the R-D model equations [125], Alam performed numerical simulations for newer CMOS technologies [126,25], and finally Mahapatra verified the applicability of the model [118,121]. Quite recently, Grasser et al. proposed a coupled modeling solution of the R-D model with the semiconductor current transport equations [127]. The R-D model states that the NBTI induced shift in p-MOSFET parameters is driven by breaking of hydrogen-passivated silicon bonds at the substrate interface and subsequent diffusion of hydrogen. The formation of interface traps is described by two coupled differential equations:

$\displaystyle \frac{\partial N_{it}(t)}{\partial t}$ $\displaystyle =\! k_{f} \![N_{0} - N_{it}(t)] - k_{r} \!N_{it}(t) C_{H}(x\!=\!0,t)  ,$ (5.1)
$\displaystyle \frac{\partial N_{it}(t)}{\partial t}$ $\displaystyle =\! - D \frac{\partial C_{H}(x,t)}{\partial x}\!\Big\vert _{x=0} + \frac{\delta}{2}\frac{\partial C_{H}(x,t)}{\partial t}  .$ (5.2)

Figure 5.2: Schematic description of the R-D model (left) and possible mechanism for breaking interfacial Si-H bonds by inversion-layer holes (right).

Equation (5.1) states that the $ N_{it}$ generation is determined by a chemical hydrogen release reaction with a constant dissociation rate $ k_f$, when the p-MOSFET is biased in inversion. When the transistor is switched off, the forward rate $ k_{f}$ becomes zero and the reverse rate $ k_{r}$ stays unchanged. The parameter $ N_{0}$ denotes the total Si-H bond density at the interface before stress. Equation (5.2) is obtained by integration of the standard diffusion equation across the silicon/oxide interface with a thickness $ \delta$. The diffusion coefficient $ D$ is the average diffusivity of the diffusing hydrogen species (atomic and molecular hydrogen). Note that the generated interface traps $ N_{it}(t)$ are equal to the number of released hydrogen atoms at any given time $ t$.

The left sketch in Fig. 5.2 shows that released hydrogen diffuses into the gate oxide during NBT stress and returns back to the interface when stress is removed. The active region of the NBTI mechanism is uniformly distributed over the channel according to a one-dimensional problem. The right sketch depicts that a hole can tunnel to a Si-H bond during inversion of the p-MOSFET and it can take one electron of the covalent bonding away. After that, the hydrogen atom diffuses away with its electron and leaves a positively charged interface trap behind.
The discretization of the differential equations (5.1) and (5.2) is based on a one-dimensional finite differences method. The simulation domain for the diffusing hydrogen is the gate oxide with the boundary condition of an adjustable reflecting and absorbing wall at the oxide/poly interface. The differential quotients are approximated with differences using the spatial and temporal increments $ h$ and $ \Delta t$, respectively. Grid points $ (x_i, \!t_j)$ with resolution $ m \!\!= \!\!\frac{T_{ox}}{h}$ are used for an oxide thickness $ T_{ox}$, and $ x_i \!=i \!h$ for $ i \!= \!0, \!1,\ldots, \!m$ and $ t_j \!=j \!\Delta t$ for $ j \!= \!0, \!1,\ldots$
We are solving for the next time step $ (n \!+ \!1)$ in order to calculate the hydrogen diffusion profile $ C_{H,i}^j \!= \!C_H(x_i, \!t_j)$ and the interface trap concentration $ N_{it}^j \!= \!N_{it}(t_j)$ at the next instant according to the following equations:

$\displaystyle C_{H,0}^{n+1}$ $\displaystyle = C_{H,0}^n + \frac{2 \!\Delta t \!\gamma^n}{\delta} + \frac{2 \!\lambda \!h}{\delta} \left( C_{H,1}^n - C_{H,0}^n \right)  ,$ (5.3)
$\displaystyle N_{it}^{n+1}$ $\displaystyle = N_{it}^{n}  + \gamma^n \!\Delta t  ,$ (5.4)
$\displaystyle \gamma^n$ $\displaystyle = k_{f} \left( N_{0} - N_{it}^n \right) - k_{r}  N_{it}^n  C_{H,0}^n  ,$ (5.5)
$\displaystyle \lambda$ $\displaystyle = \frac{D \Delta t}{h^2}  .$ (5.6)

The dimensionless parameter $ \lambda$ includes the ratio of the temporal and spatial discretization step, whereby stability and convergence is ensured for the interval $ 0 < \lambda \leq 0.5$ [128].

Fig. 5.3 compares the numerical solution of the calibrated R-D model for DC and AC operation to experimental data of the investigated 90nm p-MOSFET. The $ V_T$ degradation under static and dynamic NBT stress was simulated with the same model parameter set, which includes $ k_{f} \!= \!0.47 \!\mathrm{s}^{-1}$, $ k_{r} \!= \!2.8 \!\cdot\!10^{-19}\mathrm{cm}^3\mathrm{s}^{-1}$, $ N_{0} \!= \!6.11 \!\!\cdot\!10^{11}\mathrm{cm}^{-2}$, and $ \delta\! =\! 0.2$nm.

Chakravarthi et al. found that the atomic hydrogen model exhibits the typical power-law time dependence $ V_T \!\propto \!t^{0.25}$ whereas the molecular hydrogen model predicts a time dependence of $ t^{0.165}$ [117]. We found a time exponent of 0.183 for our DC data, which supports that both atomic and molecular hydrogen is present. The hydrogen distribution is calculated in the gate oxide with a physical thickness $ T_{ox} \!= \!2.4$nm for every time step. The final simulation result is the defect density $ N_{it}$ and the corresponding shift $ \Delta\!V_{T} \propto N_{it}$. Fig. 5.4 demonstrates that the calibrated model can be used to study the evolution of the MOSFET parameter degradation over time under DC and symmetric AC operation. The dynamic NBTI effect guarantees, even for a very slow switching operation, that the NBTI lifetime is improved by at least a factor of 2.

The left diagram in Fig. 5.5 shows four snapshots of hydrogen profiles $ C_H(x,t_{i})$ during the first stress phase. After 400s the transistor is switched off. The right diagram shows the corresponding profiles during relaxation. When relaxation starts, the free hydrogen near the interface can rapidly anneal broken Si-H bonds. The consumption of hydrogen near the interface creates a diffusion hole. Fig. 5.6 shows the second stress-relaxation cycle. When stress is applied again, a rapid generation of interface traps starts. After the diffusion hole is filled the generation slows down due to diffusion limited transport. In the relaxation phase hydrogen moves back to the interface again. This forward and backward movement continues in subsequent cycles.

Figure 5.3: Comparison of the numerical solution of the calibrated R-D model to measured DC and AC data (stress: 400s, relaxation: 400s).

Figure 5.4: Simulated NBTI responses to rectangular gate signals in the frequency range from DC - 10Hz for the 90nm p-MOSFET.

Figure 5.5: Snapshots of hydrogen diffusion profiles in the gate oxide during the first stress-relaxation cycle (stress: 400s, relaxation: 400s).

Figure 5.6: Simulated hydrogen distributions in the gate oxide during the second stress-relaxation cycle (stress: 400s, relaxation: 400s).

Interface traps are built up quickly during the first seconds of a stress phase (reaction-limited regime). With increasing time the hydrogen diffusion front moves towards the oxide-poly interface (diffusion-limited regime). After long times, free and bounded hydrogen densities at the silicon-oxide interface become very low, corresponding to a high level of generated interface defects. Recently, Tsujikawa and Yugami have investigated released hydrogen atoms from the substrate interface during NBT stress in a p-MOSFET with a 1.85nm thick nitrided gate dielectric [8]. Although it was expected that hydrogen can easily diffuse out in the case of ultra-thin gate dielectrics, it was found that much of the released hydrogen remains in the gate dielectric. The R-D model must take the accumulation of hydrogen in the gate oxide as well as the loss of hydrogen into the poly into account in order to predict the long-time degradation slope appropriately. We suggest to model the boundary condition at the oxide/poly interface with a more reflecting than absorbing wall. The simulated accumulation of hydrogen after 400s can be observed in the right diagram of Fig. 5.5, since the diffusion front has already reached the poly interface at $ x \!=2.4$nm at this time.

5.3 Effect of Interface Charge

The presence of donor-like interface states has three major effects on the characteristics of the degraded p-MOSFET. Firstly, the positively charged interface traps change the surface potential and hence reduce the inversion layer hole density. Secondly, the interface charge leads to a degradation in mobility due to the Coulomb scattering effect. Thirdly, the interface traps can act as generation-recombination centers, or assist in the tunneling process, and thus contribute to the gate leakage current [129].

5.3.1 Effect of Interface Charge on Surface Potential

For a MOS structure, the effect of interface charge can be described in terms of change in gate voltage which is necessary to restore the surface potential to that of zero interface charge. In other words, the interface charge density ( $ N_{it}\cdot q$) produces a threshold voltage shift $ \Delta V_{T}$ which depends mainly on the oxide capacitance per unit area, $ C_{ox}$, given by

$\displaystyle \Delta V_{T} \approx - \frac{N_{it}\cdot q}{C_{ox}}  .$ (5.7)

The effect of an arbitrary space charge $ \rho(x)$ distributed over an interface zone of thickness $ \delta$ is equivalent to a virtual sheet charge $ \sigma_{equ}$ located at the silicon/oxide interface according to

$\displaystyle \sigma_{equ} = \frac{1}{T_{ox}}  \int \limits_{0}^{ \delta} x  \rho(x) \; \mathrm{d}x  .$ (5.8)

The R-D model can be used to calculate the interface trap density $ N_{it}$ of the device which arises under NBT stress for a certain stress time. The calculated $ N_{it}$ value can then be used as input quantity for the device simulator Minimos-NT in order to analyze the effect of the generated interface traps on the drain current [130]. The simulator allows to set an interface charge $ \sigma $ at the interface between the semiconductor and the gate dielectric, which leads to a discontinuity of the dielectric flux perpendicular to the interface $ \varepsilon E_{\perp}$ according to

$\displaystyle \quad\varepsilon_1 E_{1\perp} - \varepsilon_2 E_{2\perp}  =  \sigma \quad\:\: (\mathrm{As}/\mathrm{cm^2})  .$ (5.9)

The interface charge density $ \sigma=N_{it}\cdot {q}$ can be interpreted as the number of holes trapped per $ \mathrm{cm^2}$. Fig. 5.7 shows the Minimos-NT result for the degraded drain current of a p-MOSFET at the end of the device lifetime. The simulated device has a gate dielectric of pure SiO$ _{2}$ with a thickness of $ T_{ox}=3$nm. Note that this first-order simulation considers only the electrostatic effect of the interface charge on the drain current and ignores the mobility degradation.

Figure 5.7: Simulated output characteristics of a p-MOSFET before and after NBTI degradation. A shift of $ \Delta V_{T} = -60$mV is produced by an interface trap density of $ 4.31\cdot 10^{11}$cm$ ^{-2}$ at the end of the lifetime.


5.3.2 Effect of Interface Charge on Mobility Degradation

Coulomb scattering arises due to charged centers in the gate oxide, at the interface, and due to ionized impurities. Higher interface trap densities imply higher Coulomb scattering. This dissipative process causes a large mobility degradation for lightly inverted surfaces, but the degradation decreases at higher oxide fields due to increased inversion charge screening. The impact of NBTI on mobility was investigated for a 130nm CMOS technology in [131]. This group reported that the mobility degradation has a significant contribution of approximately $ 40\%$ to the drain current degradation.

The mobility degradation is primarily large at gate voltages close to $ V_T$ and affects also the $ V_T$ shift of the device. A device model is used to derive the relationship between $ V_T$ shift and trap density $ N_{it}$ in a simplified manner [9]. In the following derivation, the absolute values of quantities are specified to describe the p-MOSFET and the subscript ``0'' denotes the initial value of a quantity before stress. The $ V_T$ shift caused by interface traps can be composed by an electrostatic part and a mobility degradation part:

$\displaystyle \Delta V_{T} = \Delta V_{T,charge} + \Delta V_{T,Coulomb}  .$ (5.10)

The pre-stress drain current is given by the well-known expression for the linear MOSFET region

$\displaystyle I_{D0} = \frac{W}{L} \mu_{0} C_{ox} \left( V_G - V_T - \frac{V_D}{2} \right) V_D  .$ (5.11)

If uniformly distributed interface traps $ N_{it}$ are introduced, they will cause a drain current degradation firstly due to a loss in mobile charge and secondly due to a degradation in mobility, which results in

$\displaystyle I_{D} = \frac{W}{L} \mu \left[ C_{ox} \left( V_G - V_T - \frac{V_D}{2} \right) - q N_{it} \right] V_D  .$ (5.12)

The mobility degradation caused by Coulomb scattering can be empirically modeled with a constant $ \alpha$ according to

$\displaystyle \mu = \frac{\mu_0} {1 + \alpha \cdot N_{it}}  .$ (5.13)

When the degradation of the transconductance $ g_m$ is relatively small, the relative degradation $ \frac{\Delta g_m}{g_{m0}}$ can be approximated by

$\displaystyle \frac{\Delta g_m}{g_{m0}} \approx \frac{\Delta g_m}{g_{m0} - \Delta g_m} = \alpha \cdot N_{it}  ,$ (5.14)

The result $ \alpha \cdot N_{it}$ in equation (5.14) is obtained by differentiating equation (5.11) and (5.12).

Since the threshold voltage $ V_T$ is defined for a fixed drain current $ I_T$ in this derivation, $ \Delta V_T$ is the difference in the gate voltage after and before NBT stress. From (5.11) to (5.14) we obtain finally an extended relationship between $ \Delta V_T$ and $ N_{it}$

$\displaystyle \Delta V_T = \left[\frac{q}{C_{ox}} + \frac{\alpha \!L \!I_T}{W \mu_0 C_{ox} V_D} \right] \cdot N_{it}  ,$ (5.15)

where the first term accounts for the reduced inversion charge and the second term for the mobility degradation. The degraded p-MOSFET has a reduced transconductance, $ g_m$, and hence a larger gate voltage $ V_G$ is required in order to reach the current level $ I_T$ which defines the threshold voltage. This results in a contribution by the mobility degradation, $ \Delta V_{T,Coulomb} \propto \Delta g_m$, on the total $ V_T$-shift $ \Delta V_T$.

5.4 Impact of NBTI Induced Degradation on the Lifetime

The NBTI driven device parameter shift ($ V_T$, $ I_{Dsat}$) over time depends significantly on the frequencies and ``on'' duty cycles which are used to drive the transistor gate. It will be shown that apart from the rectangular waveform characteristics of the gate signal the supply voltage tolerance of the chip plays also a major role for the transistor lifetime at a given temperature.

5.4.1 Analysis of Device Parameter Degradation

Throughout this work, the analysis of degradation trends for the parameters is based on numerical simulations with a calibrated R-D model. Extensions to the model were made by empirically gained relationships to allow the simulation of current degradation, as well as to include the gate voltage and frequency dependence of the NBTI effect.

Current Degradation

A relationship between the threshold voltage degradation and the current degradation is required in order to translate the calculated shift $ \Delta V_T \propto
N_{it}$ into the corresponding current reduction $ \Delta I_{Dsat}$. Cypress has measured four 90nm p-MOSFET devices at different gate voltages. Fig. 5.8 shows the found linear relationship between the $ I_{Dsat}$ shift and the $ V_{T}$ shift, which is caused by operating in a quite linear range of the $ I_D$ - $ V_G$ transfer characteristic. Note that the spread for the pre-stress parameter $ I_{Dsat0}$ of the transistors is eliminated by relating the $ I_{Dsat}$ data on the corresponding $ I_{Dsat0}$ value. A factor $ \vartheta \approx 1$ was found for the relationship between the relative current degradation and the relative $ V_T$ degradation given by

$\displaystyle \frac {\Delta I_{Dsat}}{I_{Dsat0}}\; = \;\vartheta \cdot \frac {\Delta V_T}{V_{T0}}  .$ (5.16)

Fig. 5.9 shows the impact of AC operation on the drive current degradation of the transistor. Note that the 1 : 1 relation between the relative changes of $ V_T$ and $ I_{Dsat}$ parameters implies an equal relative degradation level for both parameters.

Behavior of NBTI under AC Conditions

NBTI degradation is independent of the frequency only in the low-frequency regime up to approximately 100Hz. As the frequency is increased further the NBTI degradation decreases significantly with increasing frequency. The effect of the frequency on the $ V_T$ parameter shift is demonstrated in Fig. 5.10 for a very low frequency operation. It can be observed that the amplitude of the AC response signals decreases with increasing frequency and all signals oscillate around a similar average degradation level.

Figure 5.8: The data show a linear relationship between $ I_{Dsat}$ shift and $ V_{T}$ shift valid at least up to a 80mV-lifetime ( $ \approx 20\%$ change in threshold voltage).

Figure 5.9: Comparison of simulated and measured drive current degradation $ I_{Dsat}$ under slow AC operation at 2.4V power supply.


Figure 5.10: Simulation results for the $ V_T$ degradation during the first 1000 seconds under AC operation in the low frequency regime.

Figure 5.11: The simulations demonstrate the effect of the ``on'' duty cycle on the $ V_T$ degradation during the first 1000 seconds.

The reduction in device degradation during AC operation is mainly caused by the passivation of interface traps during the ``off'' state of the applied duty cycle of 50%. In contrast to that, Fig. 5.11 shows different average degradation levels for AC response signals at different ``on'' duty cycles. The R-D model assumes a hydrogen dissociation process with constant rate $ k_f$ which is switched on and off without a delay by the edges of the gate voltage signal. Therefore this first-order model predicts that the parameter shift does not depend on the frequency (it depends only on the duty cycle of the gate signal). However, the measured frequency dependence of NBTI at higher frequencies indicates that there is an asymmetry of the delays between dissociation and annealing. It can be speculated that a short delay exists between the availability of holes and their capture by Si-H bonds. Therefore it can be assumed that the slower starting of the dissociation process is responsible for the reduced parameter shift in the higher frequency regime. The simulation of a higher frequency signal is performed at a low reference frequency $ f_0$ and the result is corrected afterwards with the measured relative $ V_T$ shift as function of the frequency according to

Figure 5.12: Measured $ V_T$ shift at different duty cycles as a function of frequency.

$\displaystyle V_{T}(f) = V_{T}(f_{0}) \left(\frac{\;f\;}{f_{0}}\right)^{\!-0.03323}  .$ (5.17)

Fig. 5.12 demonstrates that the NBTI induced $ V_T$ shift is significantly reduced for higher frequencies or smaller ``on'' duty cycles. Discussions at the IEEE Integrated Reliability Workshop (IRW) in 2005 revealed that the parameter degradation is further reduced above 100MHz.

Electric Field Dependence of NBTI Degradation

Devices of different gate oxide thickness $ T_{ox}$ show the same parameter degradation at the same oxide field $ E_{ox}$. The dissociation rate $ k_f$ is determined by the available surface hole density $ p$ which is controlled by $ E_{ox}$ during inversion. Surface holes can tunnel to the Si-H bonds located in the SiO $ _{\mathrm{x}}$ interface zone governed by the field $ E_{ox}$. It can be speculated that the amount of Si-H bonds $ N_0$ at the interface which can be reached by this stochastic tunneling process increases with the oxide field. Therefore the parameters $ k_f$ and $ N_0$ of the R-D model depend on the gate voltage. It was found in [132] that the parameter degradation has a tendency to saturate with increasing stress time, but the saturation value becomes higher under higher stress voltage condition. Fig. 5.13 shows a good agreement between simulation results and experimental data in the whole measurement range from -1.5V up to -2.7V. The $ V_T$ degradation depends on the gate voltage in a nonlinear manner, in particular in the higher stress-voltage regime.

Figure 5.13: Simulated and measured $ V_T$ shift at different negative gate bias.


5.4.2 Analysis of NBTI Lifetime

Currently there is no clear specification for the characterization of NBTI lifetime across industry. Companies use various stress conditions for NBTI measurements as well as different electrical stability requirements for their lifetime projections. A reasonable failure criterion for the 90nm CMOS technology is, for instance, to tolerate a maximum shift of 10% for the key device parameters $ V_T$ and $ I_{Dsat}$ at 125$ ^\circ $C. The maximum tolerable parameter shift is determined by process-related parameter fluctuations like random dopant fluctuations or circuit applications. Fig. 5.14 shows long-time simulations for the lifetime estimation at a supply voltage of 1.5V under DC and AC operation up to 10MHz. It can be observed that the diffusion-limited regime is reached rapidly which is characterized by a reduced slope of the $ V_T$ shift over time. Note that the worst-case is assumed for the degradation slope at large stress times where no significant further reduction in the slope occurs.

Figure 5.14: Long-time simulations for the $ V_T$ shift at chip operating frequencies in the MHz-range at a power supply of 1.5V.

Figure 5.15: Simulated lifetime extension under AC operation for slightly different supply voltages of the chip.

The lifetime extension of the p-MOSFET under higher frequency operation is analyzed quantitatively in Fig. 5.15. The lifetime at a typical power supply of 1.45V and a frequency of 10MHz is ten times higher than the DC lifetime. Due to the high voltage sensitivity of NBTI the impact of a power supply tolerance of $ \mathrm{\pm \!50mV}$ is investigated. The device lifetime is defined here by a $ V_T$ shift of 80mV. The simulation predicts that the AC lifetime at 10MHz lies between six times (for 1.5V supply) and twenty times (for 1.4V) of the DC lifetime at 1.45V operation. A remarkable result is also that the lowering of the 1.5V supply by only 50mV improves the NBTI lifetime by a factor of 1.8.

The NBTI mechanism was systematically investigated for a 90nm CMOS technology in this section. Experiments for different gate voltages, frequencies, and duty cycles were performed in cooperation with Cypress to analyze the device parameter degradation of the p-MOSFET. It turned out that the R-D model is well suited to explain static and dynamic experimental data. The gate voltage and frequency dependence of NBTI was included by means of an empirical relationship. All measured data could be well reproduced by the performed numerical simulations. The presented simulation approach allows, on a physically rigorous basis, to predict the p-MOSFET lifetime which depends strongly on the applied stress conditions.

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R. Wittmann: Miniaturization Problems in CMOS Technology: Investigation of Doping Profiles and Reliability