IBM began to developed metallization technologies based on copper in the 1990s [2, 81].
One benefit, as shown in Table 1.1, is the reduced resistance compared to aluminium of about 40%. The process of fabrication had to be modified as there is no reactive ion etching process for mass-production, quite contrary to aluminium . Therefore the fabrication process for aluminium fabrication is adopted in the following way. After the deposition of the silicon oxide a second oxide layer is grown. This oxide is covered with a photoresist which in turn is exposed to UV light for the pattern transfer from the mask and subsequently dissoluted. After the etching process the oxide remains
only at those locations where no copper should be located and the copper is deposited into the trenches and forms a layer at the top of the wafer. By chemical-mechanical polishing the top layer is removed and only the filled trenches remain. For the isolation another oxide layer is deposited and the steps described are repeated until the last metallization layer is formed . This process is comparable to the tungsten via creation used in the aluminium fabrication process as discussed before. Therefore, the processes forming the vias and the lines are very similar which enables the reduction of the process steps by saving one isolation oxide deposition, diffusion barrier, copper deposition, and planarisation step [69, 149].
The dual-damascene process takes advantage of of the possibility to omit several process steps and is explained in the following. First an inter-level dielectric (ILD) layer is deposited on the wafer, followed by a photolithographic pattern transfer, the dissolution of the exposed photoresist, and etching of the via holes. By depositing another photoresist and exposing it to UV light masked by the line patterns the structure of the lines is transferred. After dissolution of the photoresist and etching, the trenches of the lines are etched into the ILD and the via holes are further etched to the bottom of the layer. The last steps are a deposition of the barrier layer and the copper, filling the vias and trenches, as well as forming a layer at the top of the wafer which is removed by chemical-mechanical polishing and covered by a non-conductive diffusion-barrier layer (eg. ) . Figure 1.2 compares the single- to the dual-damascene structure. In the dual-damascene structure the inter-via dielectric (IVD) layer is missing giving an idea of the reduction of the fabrication steps.« PreviousUpNext »Contents