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Publications Markus Karner

76 records

Publications in Scientific Journals

16.   Filipovic, L., Baumgartner, O., Klemenschits, X., Piso, J., Bobinac, J., Reiter, T., Strof, G., Rzepa, G., Stanojevic, Z., Karner, M. (2023).
DTCO Flow for Air Spacer Generation and Its Impact on Power and Performance at N7.
Solid-State Electronics, 199, Article 108527. https://doi.org/10.1016/j.sse.2022.108527 (reposiTUm)

15.   Bobinac, J., Reiter, T., Piso, J., Klemenschits, X., Baumgartner, O., Stanojevic, Z., Strof, G., Karner, M., Filipovic, L. (2023).
Effect of Mask Geometry Variation on Plasma Etching Profiles.
Micromachines, 14(3), Article 665. https://doi.org/10.3390/mi14030665 (reposiTUm)

14.   Stanojević, Z., Baumgartner, O., Filipović, L., Kosina, H., Karner, M., Kernstock, C., Prause, P. (2015).
Consistent Low-Field Mobility Modeling for Advanced MOS Devices.
Solid-State Electronics, 112, 37–45. https://doi.org/10.1016/j.sse.2015.02.008 (reposiTUm)

13.   Illarionov, Yu. Yu., Vexler, M. I., Karner, M., Tyaginov, S. E., Cervenka, J., Grasser, T. (2015).
TCAD Simulation of Tunneling Leakage Current in CaF2/Si(111) MIS Structures.
Current Applied Physics, 15(2), 78–83. https://doi.org/10.1016/j.cap.2014.10.015 (reposiTUm)

12.   Baumgartner, O., Stanojevic, Z., Schnass, K., Karner, M., Kosina, H. (2013).
VSP - A Quantum-Electronic Simulation Framework.
Journal of Computational Electronics, 12(4), 701–721. https://doi.org/10.1007/s10825-013-0535-y (reposiTUm)

11.   Baumgartner, O., Karner, M., Sverdlov, V., Kosina, H. (2010).
Electron Subband Structure in Strained Silicon UTB Films From the Hensel-Hasegawa-Nakayama Model - Part 2 Efficient Self-Consistent Numerical Solution of the k.p Schrödinger Equation.
Solid-State Electronics, 54(2), 143–148. https://doi.org/10.1016/j.sse.2009.12.010 (reposiTUm)

10.   Tyaginov, S. E., Starkov, I., Triebl, O., Cervenka, J., Jungemann, C., Carniello, S., Park, J. M., Enichlmair, H., Karner, M., Kernstock, C., Seebacher, E., Minixhofer, R., Ceric, H., Grasser, T. (2010).
Interface Traps Density-Of-States as a Vital Component for Hot-Carrier Degradation Modeling.
Microelectronics Reliability, 50, 1267–1272. (reposiTUm)

9.   Vasicek, M., Cervenka, J., Wagner, M., Karner, M., Grasser, T. (2008).
A 2D Non-Parabolic Six-Moments Model.
Solid-State Electronics, 52(10), 1606–1609. https://doi.org/10.1016/j.sse.2008.06.010 (reposiTUm)

8.   Goes, W., Karner, M., Sverdlov, V., Grasser, T. (2008).
Charging and Discharging of Oxide Defects in Reliability Issues.
IEEE Transactions on Device and Materials Reliability, 8(3), 491–500. https://doi.org/10.1109/tdmr.2008.2005247 (reposiTUm)

7.   Vasicek, M., Cervenka, J., Wagner, M., Karner, M., Grasser, T. (2008).
Parameter Modeling for Higher-Order Transport Models in UTB SOI MOSFETs.
Journal of Computational Electronics, 7(3), 168–171. https://doi.org/10.1007/s10825-008-0239-x (reposiTUm)

6.   Karner, M., Gehring, A., Holzer, S., Pourfath, M., Wagner, M., Goes, W., Vasicek, M., Baumgartner, O., Kernstock, C., Schnass, K., Zeiler, G., Grasser, T., Kosina, H., Selberherr, S. (2007).
A Multi-Purpose Schrödinger-Poisson Solver for TCAD Applications.
Journal of Computational Electronics, 6(1–3), 179–182. https://doi.org/10.1007/s10825-006-0077-7 (reposiTUm)

5.   Holzer, S., Sheikholeslami, A., Karner, M., Grasser, T., Selberherr, S. (2007).
Comparison of Deposition Models for a TEOS LPCVD Process.
Microelectronics Reliability, 47(4–5), 623–625. https://doi.org/10.1016/j.microrel.2007.01.058 (reposiTUm)

4.   Palestri, P., Barin, N., Brunel, D., Busseret, C., Campera, A., Childs, P., Driussi, F., Fiegna, C., Fiori, G., Gusmeroli, R., Iannaccone, G., Karner, M., Kosina, H., Lacaita, A. L., Langer, E., Majkusiak, B., Monzio Compagnoni, C., Poncet, A., Sangiorgi, E., … Walczak, J. (2007).
Comparison of Modeling Approaches for the Capacitance-Voltage and Current-Voltage Characteristics of Advanced Gate Stacks.
IEEE Transactions on Electron Devices, 54(1), 106–114. https://doi.org/10.1109/ted.2006.887226 (reposiTUm)

3.   Wagner, M., Karner, M., Cervenka, J., Vasicek, M., Kosina, H., Holzer, S., Grasser, T. (2007).
Quantum Correction for DG MOSFETs.
Journal of Computational Electronics, 5(4), 397–400. https://doi.org/10.1007/s10825-006-0032-7 (reposiTUm)

2.   Karner, M., Gehring, A., Wagner, M., Entner, R., Holzer, S., Goes, W., Vasicek, M., Grasser, T., Kosina, H., Selberherr, S. (2007).
VSP - A Gate Stack Analyzer.
Microelectronics Reliability, 47(4–5), 704–708. https://doi.org/10.1016/j.microrel.2007.01.059 (reposiTUm)

1.   Karner, M., Gehring, A., Kosina, H. (2006).
Efficient Calculation of Lifetime Based Direct Tunneling Through Stacked Dielectrics.
Journal of Computational Electronics, 5(2–3), 161–165. https://doi.org/10.1007/s10825-006-8837-y (reposiTUm)

Contributions to Books

2.   Karner, M., Gehring, A., Holzer, S., Kosina, H., Selberherr, S. (2006).
Efficient Calculation of Lifetime Based Direct Tunneling Through Stacked Dielectrics.
In S. Kar, S. De Gendt, M. Houssa, D. Landheer, D. Misra, W. Tsai (Eds.), ECS Transactions (pp. 693–703). ECS Transactions. https://doi.org/10.1149/1.2209316 (reposiTUm)

1.   Karner, M., Holzer, S., Gös, W., Vasicek, M., Wagner, M., Kosina, H., Selberherr, S. (2006).
Numerical Analysis of Gate Stacks.
In S. Kar, S. De Gendt, M. Houssa, H. Iwai, D. Landheer, D. Misra (Eds.), ECS Transactions (pp. 299–308). ECS Transactions. https://doi.org/10.1149/1.2355721 (reposiTUm)

Talks and Poster Presentations (with Proceedings-Entry)

50.   Filipovic, L., Baumgartner, O., Piso, J., Bobinac, J., Reiter, T., Strof, G., Rzepa, G., Stanojevic, Z., Karner, M. (2022).
DTCO Flow for Air Spacer Generation and Its Impact on Power and Performance at N7.
In SISPAD 2022: International Conference on Simulation of Semiconductor Processes and Devices - Conference Abstract Booklet (pp. 34–35), Granada, Spain. (reposiTUm)

49.   Bobinac, J., Reiter, T., Piso, J., Klemenschits, X., Baumgartner, O., Stanojevic, Z., Strof, G., Karner, M., Filipovic, L. (2022).
Impact of Mask Tapering on SF6/O2 Plasma Etching.
In Microelectronic Devices and Technologies: Proceedings of the 4rd International Conference on Microelectronic Devices and Technologies (MicDAT '2022) (pp. 90–94), Corfu, Greece. (reposiTUm)

48.   Karner, M., Baumgartner, O., Stanojevic, Z., Schanovsky, F., Strof, G., Kernstock, C., Karner, H., Rzepa, G., Grasser, T. (2016).
Vertically Stacked Nanowire MOSFETs for Sub-10nm Nodes: Advanced Topography, Device, Variability, and Reliability Simulations.
In 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. https://doi.org/10.1109/iedm.2016.7838516 (reposiTUm)

47.   Baumgartner, O., Filipovic, L., Kosina, H., Karner, M., Stanojevic, Z., Cheng-Karner, H. (2015).
Efficient Modeling of Source/Drain Tunneling in Ultra-Scaled Transistors.
In 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, United States. https://doi.org/10.1109/sispad.2015.7292294 (reposiTUm)

46.   Demel, H., Stanojevic, Z., Karner, M., Rzepa, G., Grasser, T. (2015).
Expanding TCAD Simulations From Grid to Cloud.
In 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, United States. https://doi.org/10.1109/sispad.2015.7292290 (reposiTUm)

45.   Karner, M., Stanojevic, Z., Kernstock, C., Baumgartner, O., Cheng-Karner, H. (2015).
Hierarchical TCAD Device Simulation of FinFETs.
In 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, United States. https://doi.org/10.1109/sispad.2015.7292308 (reposiTUm)

44.   Kernstock, C., Stanojevic, Z., Baumgartner, O., Karner, M. (2015).
Layout-Based TCAD Device Model Generation.
In 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, United States. https://doi.org/10.1109/sispad.2015.7292293 (reposiTUm)

43.   Stanojevic, Z., Baumgartner, O., Karner, M., Filipovic, L., Kernstock, C., Kosina, H. (2014).
Advanced Numerical Methods for Semi-Classical Transport Simulation in Ultra-Narrow Channels.
In Abstracts of The 18th European Conference on Mathematics for Industry (p. 1), Taormina, Italy. (reposiTUm)

42.   Stanojevic, Z., Baumgartner, O., Karner, M., Filipovic, L., Kernstock, C., Kosina, H. (2014).
Full-Band Modeling of Mobility in P-Type FinFETs.
In 2014 IEEE Silicon Nanoelectronics Workshop (pp. 83–84), Honolulu. (reposiTUm)

41.   Stanojevic, Z., Filipovic, L., Baumgartner, O., Karner, M., Kernstock, C., Kosina, H. (2014).
Full-Band Transport in Ultra-Narrow P-Type Si Channels: Field, Orientation, Strain.
In Proc.Intl.Conf.on Ultimate Integration on Silicon (ULIS) (p. 4), Bologna, Austria. (reposiTUm)

40.   Baumgartner, O., Stanojevic, Z., Filipovic, L., Grill, A., Grasser, T., Kosina, H., Karner, M. (2014).
Investigation of Quantum Transport in Nanoscaled GaN High Electron Mobility Transistors.
In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan. https://doi.org/10.1109/sispad.2014.6931577 (reposiTUm)

39.   Stanojevic, Z., Baumgartner, O., Karner, M., Filipovic, L., Kernstock, C., Kosina, H. (2014).
On the Validity of Momentum Relaxation Time in Low-Dimensional Carrier Gases.
In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan. https://doi.org/10.1109/sispad.2014.6931593 (reposiTUm)

38.   Rzepa, G., Goes, W., Rott, G., Rott, K., Karner, M., Kernstock, C., Kaczer, B., Reisinger, H., Grasser, T. (2014).
Physical Modeling of NBTI: From Individual Defects to Devices.
In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Yokohama, Japan. https://doi.org/10.1109/sispad.2014.6931568 (reposiTUm)

37.   Stanojevic, Z., Karner, M., Kosina, H. (2013).
Exploring the Design Space of Non-Planar Channels: Shape, Orientation, and Strain.
In 2013 IEEE International Electron Devices Meeting, San Francisco, CA, USA. https://doi.org/10.1109/iedm.2013.6724618 (reposiTUm)

36.   Stanojevic, Z., Baumgartner, O., Schnass, K., Karner, M., Kosina, H. (2013).
VSP - A Quantum Simulator for Engineering Applications.
In Book of Abstracts of the International Workshop on Computational Electronics (IWCE) (pp. 132–133), Urbana-Champaign, IL, USA. (reposiTUm)

35.   Tyaginov, S., Starkov, I., Triebl, O., Karner, M., Kernstock, C., Jungemann, C., Enichlmair, H., Park, J., Grasser, T. (2012).
Impact of Gate Oxide Thickness Variations on Hot-Carrier Degradation.
In 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore. https://doi.org/10.1109/ipfa.2012.6306265 (reposiTUm)

34.   Bina, M., Triebl, O., Schwarz, B., Karner, M., Kaczer, B., Grasser, T. (2012).
Simulation of Reliability on Nanoscale Devices.
In 2012 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (pp. 109–112), Denver, Colorado, United States. (reposiTUm)

33.   Stanojevic, Z., Karner, M., Schnass, K., Kernstock, C., Baumgartner, O., Kosina, H. (2011).
A Versatile Finite Volume Simulator for the Analysis of Electronic Properties of Nanostructures.
In 2011 International Conference on Simulation of Semiconductor Processes and Devices, Osaka, Japan. https://doi.org/10.1109/sispad.2011.6035089 (reposiTUm)

32.   Starkov, I., Tyaginov, S., Triebl, O., Cervenka, J., Jungemann, C., Carniello, S., Park, J., Enichlmair, H., Karner, M., Kernstock, C., Seebacher, E., Minixhofer, R., Ceric, H., Grasser, T. (2010).
Analysis of Worst-Case Hot-Carrier Conditions for High Voltage Transistors Based on Full-Band Monte-Carlo Simulations.
In Proceedings of the 17th International Symposium on the Physical, Failure Analysis of Integrated Circuits (pp. 139–144), Singapore. (reposiTUm)

31.   Tyaginov, S., Starkov, I., Triebl, O., Cervenka, J., Jungemann, C., Carniello, S., Park, J., Enichlmair, H., Karner, M., Kernstock, C., Seebacher, E., Minixhofer, R., Ceric, H., Grasser, T. (2010).
Hot-Carrier Degradation Modeling Using Full-Band Monte-Carlo Simulations.
In Proceedings of the 17th International Symposium on the Physical, Failure Analysis of Integrated Circuits (pp. 341–345), Singapore. (reposiTUm)

30.   Tyaginov, S., Starkov, I., Triebl, O., Cervenka, J., Jungemann, C., Carniello, S., Park, J., Enichlmair, H., Karner, M., Kernstock, C., Seebacher, E., Minixhofer, R., Ceric, H., Grasser, T. (2010).
Interface Traps Density-Of-States as a Vital Component for Hot-Carrier Degradation Modeling.
In Proceedings of the 21st European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis (p. 3), Maastricht. (reposiTUm)

29.   Goes, W., Grasser, T., Karner, M., Kaczer, B. (2009).
A Model for Switching Traps in Amorphous Oxides.
In 2009 International Conference on Simulation of Semiconductor Processes and Devices, San Diego, CA, United States. https://doi.org/10.1109/sispad.2009.5290226 (reposiTUm)

28.   Baumgartner, O., Karner, M., Sverdlov, V., Kosina, H. (2009).
Numerical Quadrature of the Subband Distribution Functions in Strained Silicon UTB Devices.
In 2009 13th International Workshop on Computational Electronics, Urbana-Champaign, IL, USA. https://doi.org/10.1109/iwce.2009.5091131 (reposiTUm)

27.   Baumgartner, O., Karner, M., Sverdlov, V., Kosina, H. (2009).
Numerical Study of the Electron Subband Structure in Strained Silicon UTB Devices.
In EUROSOI 2009 Conference Proceedings (pp. 57–58), Granadea, Spanien, Austria. (reposiTUm)

26.   Gös, W., Karner, M., Sverdlov, V., Grasser, T. (2008).
A Rigorous Model for Trapping and Detrapping in Thin Gate Dielectrics.
In Proceedings 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits (pp. 249–254), Singapore. (reposiTUm)

25.   Vasicek, M., Cervenka, J., Karner, M., Grasser, T. (2008).
Consistent Higher-Order Transport Models for SOI MOSFETs.
In 2008 International Conference on Simulation of Semiconductor Processes and Devices, Kanagawa, Japan. https://doi.org/10.1109/sispad.2008.4648254 (reposiTUm)

24.   Baumgartner, O., Schwaha, P., Karner, M. (2008).
Coupling of Non-Equilibrium Green’s Function and Wigner Function Approaches.
In 2008 International Conference on Simulation of Semiconductor Processes and Devices, Kanagawa, Japan. https://doi.org/10.1109/sispad.2008.4648308 (reposiTUm)

23.   Goes, W., Karner, M., Tyaginov, S., Hehenberger, P., Grasser, T. (2008).
Level Shifts and Gate Interfaces as Vital Ingredients in Modeling of Charge Trapping.
In 2008 International Conference on Simulation of Semiconductor Processes and Devices, Kanagawa, Japan. https://doi.org/10.1109/sispad.2008.4648239 (reposiTUm)

22.   Baumgartner, O., Karner, M., Kosina, H. (2008).
Modeling of High-K-Metal-Gate-Stacks Using the Non-Equilibrium Green’s Function Formalism.
In 2008 International Conference on Simulation of Semiconductor Processes and Devices, Kanagawa, Japan. https://doi.org/10.1109/sispad.2008.4648310 (reposiTUm)

21.   Vasicek, M., Cervenka, J., Wagner, M., Karner, M., Grasser, T. (2007).
A 2d-Non-Parabolic Six Moments Model.
In 2007 International Semiconductor Device Research Symposium (p. 2), College Park, MD, USA. (reposiTUm)

20.   Baumgartner, O., Karner, M., Holzer, S., Pourfath, M., Grasser, T., Kosina, H. (2007).
Adaptive Energy Integration of Non-Equilibrium Green's Functions.
In NSTI Nanotech Proceedings (pp. 145–148), Anaheim, Austria. (reposiTUm)

19.   Karner, M., Baumgartner, O., Pourfath, M., Vasicek, M., Kosina, H. (2007).
Investigation of a MOSCAP Using NEGF.
In 2007 International Semiconductor Device Research Symposium (p. 2), College Park, MD, USA. (reposiTUm)

18.   Vasicek, M., Karner, M., Ungersboeck, E., Wagner, M., Kosina, H., Grasser, T. (2007).
Modeling of Macroscopic Transport Parameters in Inversion Layers.
In Simulation of Semiconductor Processes and Devices 2007 (pp. 201–204), Vienna, Austria. https://doi.org/10.1007/978-3-211-72861-1_48 (reposiTUm)

17.   Vasicek, M., Cervenka, J., Karner, M., Wagner, M., Grasser, T. (2007).
Parameter Modeling for Higher-Order Transport Models in UTB SOI MOSFETs.
In Book of Abstracts of the International Workshop on Computational Electronics (IWCE) (pp. 96–97), Urbana-Champaign, IL, USA. (reposiTUm)

16.   Karner, M., Wagner, M., Grasser, T., Kosina, H. (2006).
A Physically Based Quantum Correction Model for DG MOSFETs.
In San Francisco 2006 MRS Meeting Abstracts (pp. 104–105), San Francisco. (reposiTUm)

15.   Holzer, S., Wagner, M., Sheikholeslami, A., Karner, M., Span, G., Grasser, T., Selberherr, S. (2006).
An Extendable Multi-Purpose Simulation and Optimization Framework for Thermal Problems in TCAD Applications.
In Collection of Papers Presented at the 12th International Workshop on Thermal Investigation of ICs and Systems (pp. 239–244), Nice. (reposiTUm)

14.   Holzer, S., Sheikholeslami, A., Karner, M., Grasser, T. (2006).
Comparison of Deposition Models for TEOS CVD Process.
In WODIM 2006 14th Workshop on Dielectrics in Microelectronics Workshop Programme and Abstracts (pp. 158–159), Catania. (reposiTUm)

13.   Karner, M., Gehring, A., Holzer, S., Wagner, M., Kosina, H. (2006).
Continuum Versus Quasi-Bound State Tunneling in Novel Device Architectures.
In Abstracts IEEE 2006 Silicon Nanoelectronics Workshop (pp. 161–162), Honolulu. (reposiTUm)

12.   Karner, M., Gehring, A., Holzer, S., Kosina, H. (2006).
Efficient Calculation of Quasi-Bound States for the Simulation of Direct Tunneling.
In Large-Scale Scientific Computing: 5th International Conference, LSSC 2005 (pp. 572–577), Sozopol, Bulgaria. https://doi.org/10.1007/11666806_65 (reposiTUm)

11.   Karner, M., Holzer, S., Vasicek, M., Gös, W., Wagner, M., Kosina, H., Selberherr, S. (2006).
Numerical Analysis of Gate Stacks.
In 210th ECS Meeting (p. 1), Cancun. (reposiTUm)

10.  M. Wagner, T. Grasser, M. Karner, H. Kosina:
"Quantum Correction for DG MOSFETs";
Poster: International Workshop on Computational Electronics (IWCE), Vienna, Austria; 2006-05-25 - 2006-05-27; in: "Book of Abstracts of the International Workshop on Computational Electronics (IWCE)", (2006), ISBN: 3-901578-16-1; 87 - 88.

9.   Karner, M., Ungersboeck, E., Gehring, A., Holzer, S., Kosina, H., Selberherr, S. (2006).
Strain Effects on Quasi-Bound State Tunneling in Advanced SOI CMOS Technologies.
In 2006 International Conference on Simulation of Semiconductor Processes and Devices, Monterey, California, United States. https://doi.org/10.1109/sispad.2006.282898 (reposiTUm)

8.   Holzer, S., Hollauer, C., Ceric, H., Karner, M., Grasser, T., Langer, E., Selberherr, S. (2006).
Three-Dimensional Transient Interconnect Analysis With Regard to Mechanical Stress.
In Proceedings 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 154–157), Singapore. (reposiTUm)

7.   Karner, M., Gehring, A. (2006).
VSP - A Multi-Purpose Schrödinger-Poisson Solver for TCAD Applications.
In Book of Abstracts of the International Workshop on Computational Electronics (IWCE) (pp. 255–256), Urbana-Champaign, IL, USA. (reposiTUm)

6.   Karner, M., Gehring, A., Wagner, M., Entner, R., Holzer, S., Gös, W., Vasicek, M., Grasser, T., Kosina, H., Selberherr, S. (2006).
VSP-A Gate Stack Analyzer.
In WODIM 2006 14th Workshop on Dielectrics in Microelectronics Workshop Program and Abstracts (pp. 101–102), Catania. (reposiTUm)

5.   Karner, M., Gehring, A., Kosina, H. (2005).
Efficient Calculation of Life Time Based Direct Tunneling Through Stacked Dielectrics.
In 15th Workshop on Modelling and Simulation of Electron Devices (pp. 97–98), Pisa, Austria. (reposiTUm)

4.   Karner, M., Gehring, A., Kosina, H., Selberherr, S. (2005).
Efficient Calculation of Quasi-Bound State Tunneling in CMOS Devices.
In 2005 International Conference On Simulation of Semiconductor Processes and Devices, Tokyo, Japan. https://doi.org/10.1109/sispad.2005.201466 (reposiTUm)

3.   Karner, M., Gehring, A., Holzer, S., Kosina, H., Selberherr, S. (2005).
Efficient Calculation of Quasi-Bound State Tunneling Through Stacked Dielectrics.
In 208th ECS Meeting (p. 1), Honolulu, Austria. (reposiTUm)

2.   Karner, M., Gehring, A., Holzer, S., Kosina, H. (2005).
On the Efficient Calculation of Quasi-Bound States for the Simulation of Direct Tunneling.
In Proceedings of the International Conference on Large-Scale Scientific Computations (LSSC) (pp. 33–34), Sozopol, Bulgaria. (reposiTUm)

1.   Wagner, M., Karner, M., Grasser, T. (2005).
Quantum Correction Models for Modern Semiconductor Devices.
In Proceedings of the XIII International Workshop on Semiconductor Devices (pp. 458–461), New Dehli. (reposiTUm)

Diploma and Master Theses (authored and supervised)

5.   Demel, H. (2016).
Autonom Skalierendes, Verteiltes Simulationsframework Für TCAD-Anwendungen
 Technische Universität Wien. https://doi.org/10.34726/hss.2016.23969 (reposiTUm)

4.  C. Kernstock:
"Design and Implementation of TCAD Environment Tools";
Supervisor: H. Kosina, M. Karner; Institut für Mikroelektronik, 2008; final examination: 2008-11-28.

3.  P. Prause:
"Design and Integration of Distributed Computing Concepts in a TCAD Framework";
Supervisor: E. Langer, M. Karner; Institut für Mikroelektronik, 2008; final examination: 2008-10-09.

2.  O. Baumgartner:
"Simulation of Quantum Transport Using the Non-Equilibrium Green´s Functions Formalism";
Supervisor: T. Grasser, M. Karner; Institut für Mikroelektronik, 2007; final examination: 2007-01-18.

1.  M. Karner:
"Multi-Dimensional Simulation of Closed Quantum Systems";
Supervisor: T. Grasser, A. Gehring; Institut für Mikroelektronik, 2004.

Scientific Reports

3.   Grasser, T., Karner, M., Kernstock, C., Kosina, H., Triebl, O. (2010).
Customized Software Development Report.
(reposiTUm)

2.   Karner, M., Baumgartner, O., Kosina, H. (2007).
Threshold Voltage Modeling in Strained Si Using VSP.
(reposiTUm)

1.   Ceric, H., Karner, M., Nentchev, A., Schwaha, P., Ungersböck, S. E., Selberherr, S. (2005).
VISTA Status Report December 2005.
(reposiTUm)