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Publications Alireza Sheikholeslami

32 records

Publications in Scientific Journals

6.  S. Holzer, A. Sheikholeslami, M. Karner, T. Grasser, S. Selberherr:
"Comparison of Deposition Models for a TEOS LPCVD Process";
Microelectronics Reliability, 47 (2007), 4-5; 623 - 625. https://doi.org/10.1016/j.microrel.2007.01.058

5.  M. Movahhedi, A. Abdipour, H. Ceric, A. Sheikholeslami, S. Selberherr:
"Optimization of the Perfectly Matched Layer for the Finite-Element Time-Domain Method";
IEEE Microwave and Wireless Components Letters, 17 (2007), 1; 10 - 12. https://doi.org/10.1109/LMWC.2006.887240

4.  A. Sheikholeslami, F. Parhami, H. Puchner, S. Selberherr:
"Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers";
Journal of Physics: Conference Series, 61 (2007), 1051 - 1055. https://doi.org/10.1088/1742-6596/61/1/208

3.  C. Heitzinger, A. Sheikholeslami, J.M. Park, S. Selberherr:
"A Method for Generating Structurally Aligned Grids for Semiconductor Device Simulation";
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24 (2005), 10; 1485 - 1491. https://doi.org/10.1109/TCAD.2005.852297

2.  C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr:
"Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process";
IEEE Transactions on Electron Devices, 51 (2004), 7; 1129 - 1134. https://doi.org/10.1109/TED.2004.829868

1.  A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, S. Selberherr:
"Simulation of Void Formation in Interconnect Lines";
Proceedings of SPIE, 5117 (2003), 445 - 452. https://doi.org/10.1117/12.498783

Talks and Poster Presentations (with Proceedings-Entry)

20.  S. Holzer, M. Wagner, A. Sheikholeslami, M. Karner, G. Span, T. Grasser, S. Selberherr:
"An Extendable Multi-Purpose Simulation and Optimization Framework for Thermal Problems in TCAD Applications";
Talk: Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Nice; 2006-09-27 - 2006-09-29; in: "Collection of Papers Presented at the 12th International Workshop on Thermal Investigation of ICs and Systems", (2006), ISBN: 2-9161-8704-9; 239 - 244.

19.  A. Sheikholeslami, R. Heinzl, S. Holzer, C. Heitzinger, M. Spevak, M. Leicht, O. Häberlen, J. Fugger, F. Badrieh, F. Parhami, H. Puchner, T. Grasser, S. Selberherr:
"Applications of Two- and Three-Dimensional General Topography Simulator in Semiconductor Manufacturing Processes";
Talk: Iranian Conference on Electrical Engineering (ICEE), Tehran; 2006-05-16 - 2006-05-18; in: "Proceedings of the 14th Iranian Conference on Electrical Engineering ICEE 2006", (2006), 4 pages.

18.  S. Holzer, A. Sheikholeslami, M. Karner, T. Grasser:
"Comparison of Deposition Models for TEOS CVD Process";
Talk: Workshop on Dielectrics in Microelectronics (WODIM), Catania; 2006-06-26 - 2006-06-28; in: "WODIM 2006 14th Workshop on Dielectrics in Microelectronics Workshop Programme and Abstracts", (2006), 158 - 159.

17.  A. Sheikholeslami, S. Selberherr, F. Parhami, H. Puchner:
"Planarization of Passivation Layers during Manufacturing Processes of Image Sensors";
Talk: Numerical Simulation of Optoelectronic Devices (NUSOD), Singapore; 2006-09-11 - 2006-09-14; in: "Proceedings of the 6th International Conference on Numerical Simulation of Optoelectronic Devices", (2006), ISBN: 0-7803-9755-x; 35 - 36.

16.  A. Sheikholeslami, F. Parhami, H. Puchner, S. Selberherr:
"Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers";
Talk: International Conference on Nanoscience and Technology (ICNT), Basel; 2006-07-30 - 2006-08-04; in: "International Conference on Nanoscience and Technology (ICNT 2006)", (2006), ISBN: 3-905084-71-6; 163 - 164.

15.  A. Sheikholeslami, F. Parhami, R. Heinzl, E. Al-Ani, C. Heitzinger, F. Badrieh, H. Puchner, T. Grasser, S. Selberherr:
"Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines";
Poster: International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Tokyo, Japan; 2005-09-01 - 2005-09-03; in: "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)", (2005), ISBN: 4-9902762-0-5; 187 - 190. https://doi.org/10.1109/SISPAD.2005.201504

14.  A. Sheikholeslami, S. Holzer, C. Heitzinger, M. Leicht, O. Häberlen, J. Fugger, T. Grasser, S. Selberherr:
"Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process";
Talk: PhD Research in Microelectronics and Electronics (PRIME), Lausanne; 2005-07-25 - 2005-07-28; in: "2005 PhD Research in Microelectronics and Electronics", Vol. 2 (2005), ISBN: 0-7803-9345-7; 279 - 282.

13.  A. Sheikholeslami, E. Al-Ani, R. Heinzl, C. Heitzinger, F. Parhami, F. Badrieh, H. Puchner, T. Grasser, S. Selberherr:
"Level Set Method Based General Topography Simulator and its Application in Interconnect Processes";
Poster: International Conference on Ultimate Integration of Silicon (ULIS), Bologna; 2005-04-07 - 2005-04-08; in: "ULIS 2005 6th International Conference on Ultimate Integration of Silicon", (2005), ISBN: 8890084707; 139 - 142.

12.  C. Heitzinger, A. Sheikholeslami, J. Fugger, O. Häberlen, M. Leicht, S. Selberherr:
"A Case Study in Predictive Three-Dimensional Topography Simulation Based on a Level-Set Algorithm";
Talk: Meeting of the Electrochemical Society, Electrochemical Processing in ULSI and MEMS, San Antonio; 2004-05-09 - 2004-05-13; in: "205th ECS Meeting", (2004), 132 - 142.

11.  S. Holzer, A. Sheikholeslami, S. Wagner, C. Heitzinger, T. Grasser, S. Selberherr:
"Optimization and Inverse Modeling for TCAD Applications";
Talk: Symposium on Nano Device Technology (SNDT), Hsinchu; 2004-05-12 - 2004-05-13; in: "Proceedings of the Symposium on Nano Device Technology", (2004), 113 - 116.

10.  A. Sheikholeslami, C. Heitzinger, E. Al-Ani, R. Heinzl, T. Grasser, S. Selberherr:
"Three-Dimensional Surface Evolution Using a Level Set Method";
Poster: Iranian Ph.D. Students Seminar on Computer Science, Mathematics and Statistics (ICSMS), Paris; 2004-12-01; in: "Proceedings of the Iranian Ph.D. Students Seminar on Computer Science, Mathematics and Statistics (ICSMS)", (2004).

9.  A. Sheikholeslami, C. Heitzinger, F. Badrieh, H. Puchner, S. Selberherr:
"Three-Dimensional Topography Simulation Based on a Level Set Method";
Talk: International Spring Seminar on Electronics Technology (ISSE), Sofia; 2004-05-13 - 2004-05-16; in: "Proceedings IEEE International Spring Seminar on Electronics Technology 27th ISSE 2004", IEEE, 2 (2004), ISBN: 0-7803-8422-9; 263 - 265.

8.  A. Sheikholeslami, C. Heitzinger, T. Grasser, S. Selberherr:
"Three-Dimensional Topography Simulation for Deposition and Etching Processes Using a Level Set Method";
Talk: International Conference on Microelectronics (MIEL), Nis; 2004-05-16 - 2004-05-19; in: "Proceedings of the International Conference on Microelectronics (MIEL)", (2004), ISBN: 0-7803-8166-1; 241 - 244. https://doi.org/10.1109/ICMEL.2004.1314606

7.  A. Sheikholeslami, C. Heitzinger, S. Selberherr:
"A Method for Generating Structurally Aligned Grids Using a Level Set Approach";
Talk: European Simulation Multiconference (ESM), Nottingham; 2003-06-09 - 2003-06-11; in: "Proc. 17th European Simulation Multiconference: Modelling and Simulation", (2003), ISBN: 3-936150-25-7; 496 - 501.

6.  C. Heitzinger, A. Sheikholeslami, J.M. Park, S. Selberherr:
"A Method for Generating Structurally Aligned High Quality Grids and its Application to the Simulation of a Trench Gate MOSFET";
Poster: European Solid-State Device Research Conference (ESSDERC), Estoril; 2003-09-16 - 2003-09-18; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2003), ISBN: 0-7803-7999-3; 457 - 460.

5.  A. Sheikholeslami, C. Heitzinger, S. Selberherr, F. Badrieh, H. Puchner:
"Capacitances in the Backend of a 100nm CMOS Process and their Predictive Simulation";
Poster: Informationstagung Mikroelektronik (ME), Wien; 2003-10-01 - 2003-10-02; in: "Beiträge der Informationstagung Mikroelektronik 2003", (2003), ISBN: 3-85133-030-7; 481 - 486.

4.  C. Heitzinger, A. Sheikholeslami, F. Badrieh, H. Puchner, S. Selberherr:
"Feature Scale Simulation of Advanced Etching Processes";
Talk: Meeting of the Electrochemical Society, Physical Electrochemistry, Orlando; 2003-10-12 - 2003-10-16; in: "204th ECS Meeting", (2003), ISBN: 1-56677-398-9; 1259.

3.  F. Badrieh, H. Puchner, C. Heitzinger, A. Sheikholeslami, S. Selberherr:
"From Feature Scale Simulation to Backend Simulation for a 100nm CMOS Process";
Poster: European Solid-State Device Research Conference (ESSDERC), Estoril; 2003-09-16 - 2003-09-18; in: "Proceedings of the European Solid-State Device Research Conference (ESSDERC)", (2003), ISBN: 0-7803-7999-3; 441 - 444.

2.  C. Heitzinger, A. Sheikholeslami, H. Puchner, S. Selberherr:
"Predictive Simulation of Void Formation During the Deposition of Silicon Nitride and Silicon Dioxide Films";
Talk: Meeting of the Electrochemical Society (ECS), Paris; 2003-04-26 - 2003-05-02; in: "203rd ECS Meeting", (2003), ISBN: 1-56677-347-4; 356 - 365.

1.  C. Heitzinger, A. Sheikholeslami, S. Selberherr:
"Predictive Simulation of Etching and Deposition Processes Using the Level Set Method";
Poster: International Workshop on Challenges in Predictive Process Simulation (ChiPPS), Prague; 2002-10-13 - 2002-10-17; in: "ChiPPS-2002 Challenges in Predictive Process Simulation", (2002), 65 - 66.

Doctor's Theses (authored and supervised)

1.  A. Sheikholeslami:
"Topography Simulation of Deposition and Etching Processes";
Supervisor, Reviewer: S. Selberherr, K. Riedling; Institut für Mikroelektronik, 2006; oral examination: 2006-10-06.

Diploma and Master Theses (authored and supervised)

2.  A. Sheikholeslami, C. Heitzinger, H. Puchner, F. Badrieh, S. Selberherr:
"Simulation of Void Formation in Interconnect Lines";
Talk: SPIE VLSI Circuits and Systems, Maspalomas, Spain; 2003-05-19 - 2003-05-21.

1.  A. Sheikholeslami:
"Implementierung und Untersuchung räumlicher Modelle für zeitvariante Mobilfunkkanäle";
Supervisor: H. Artes, F. Hlawatsch; Institut für Nachrichtentechnik und Hochfrequenztechnik, 2002.

Scientific Reports

3.  R. Entner, R. Heinzl, Ch. Hollauer, A. Sheikholeslami, R. Wittmann, S. Selberherr:
"VISTA Status Report June 2005";
2005; 29 pages.

2.  H. Ceric, S. Holzer, A. Sheikholeslami, T. Ayalew, R. Wittmann, S. Selberherr:
"VISTA Status Report June 2004";
2004; 28 pages.

1.  Ch. Hollauer, A. Sheikholeslami, V. Palankovski, S. Wagner, R. Wittmann, S. Selberherr:
"VISTA Status Report June 2003";
2003; 36 pages.