Introduction of sub-25nm MOSFETs is now foreseen by 2007. With such a size conventional MOSFETs demand very aggressive process steps and are affected by short channel effects, limitation in drive current, and poor switching performance. By the collaboration of industry, big Institutes and Academic labs, the prime objective of NESTOR is to provide a first assessment of three multi-gate fully depleted architectures which are the most promising to overcome these problems and are potentially scalable down to the 10nm range: the planar bonded DGMOS, the Finfet, and the "Silicon on Nothing" approach. With such a project, the European microelectronics industry will be positioned as a world-wide recognized innovation leader in terms of device architecture. A comparison of these devices to each other and to state-of-the art common MOS will allow to select the best architecture for future integration study.