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Bibliography

9

1
Mark T. Bohr, Interconnect Scaling - The Real Limiter to High Performance ULSI, IEDM 95, pp. 241-242, 1995.

2
R. Martins and S. Selberherr, Layout Data in TCAD Frameworks, ESM 96, pp. 1122-1126, 1996.

3
P. Fleischmann, R. Sabelka, A. Stach, R. Strasser and S. Selberherr, Grid Generation for Three-Dimensional Process and Device Simulation, SISPAD 96, pp. 161-166, 1996.

4
R. Bauer, M. Stiftinger and S. Selberherr, Capacitance Calculation of VLSI Multilevel Wiring Structures, VPAD, pp. 142-143, 1993.

5
M. Mukai and T. Tatsumi and N. Nakauchi and T. Kobayashi and K. Koyama and Y. Komatsu and R. Bauer and G. Rieger and S. Selberherr, The Simulation System for Three-Dimensional Capacitance and Current Density Calculation with a User Friendly GUI, Technical Report of vol.95-223, pp. 63-68, 1995.



Rainer Sabelka
1998-01-30