2015-viennacl-openmp
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- 2015/01/24 09:02
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- all_around_gate.jpeg
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- 2014/10/25 18:20
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- 2014/12/02 01:00
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- 2014/12/02 01:00
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- bulk_tri_gate.jpeg
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- 2014/10/25 11:22
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- 2014/10/25 18:21
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- 2014/12/02 00:59
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- 2014/10/25 18:21
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- 2014/10/25 18:22
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- double_gate_finfet.jpeg
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- 2014/10/25 18:23
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- 2014/12/02 00:59
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- double_gate_finfet_sim.jpg
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- 2014/12/02 00:59
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- double_gate_mosfet.jpeg
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- 2014/10/25 18:23
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- double_gate_mosfet.mp4
- 2014/09/17 07:56
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- double_gate_mosfet2.jpeg
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- 2014/10/25 18:24
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- double_gate_mosfet2.jpg
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- double_gate_mosfet2_simulated.jpg
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- 2014/10/25 18:26
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- double_gate_mosfet3.jpeg
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- 2014/10/25 18:27
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- double_gate_mosfet_meshed.jpg
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- double_gate_mosfet_simulated.jpg
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- 2014/10/25 18:29
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- double_gate_mosfet_with_asymmetric_oxide_thickness_simulated.jpg
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- 2014/10/25 18:30
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- double_gate_mosfet_with_asymmetrick_oxide_thickness_meshed.jpg
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- 2014/10/25 18:29
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- double_gate_with_asymmetric_oxide_thickness.jpeg
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- 2014/10/25 18:31
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- flexfet.jpeg
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- 2014/10/25 18:31
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- 2014/10/25 18:31
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- four_gate.jpeg
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- 2014/10/25 18:32
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- four_gate2.jpg
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- 2014/10/23 19:24
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- four_gate4.jpg
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- 2014/10/25 18:32
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- four_gate_sim2.jpg
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- 2014/10/23 19:50
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- 2014/10/25 18:33
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- fry_2015.png
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- 2015/01/24 09:18
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- 2015/01/24 09:22
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- iue-soc-info-2015.pdf
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- 2014/05/08 12:22
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- 2014/06/05 07:58
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- mosfet.jpeg
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- 2014/10/25 11:32
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- mosfet.mp4
- 2014/09/17 07:56
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- mosfet_meshed.jpg
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- 2014/10/25 11:27
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- mosfet_meshed.png
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- 2014/10/23 20:35
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- mosfet_simulated.jpg
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- 2014/10/23 20:59
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- mosfet_simulated2.jpg
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- 2014/10/25 18:41
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- omega_gate.jpeg
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- 2014/10/25 18:15
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- omega_gate_meshed.jpg
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- 2014/10/25 18:15
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- omega_gate_simulated.jpg
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- 2014/10/25 18:46
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- pi_gate.jpeg
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- 2014/10/25 18:16
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- pi_gate_meshed.jpg
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- 2014/10/25 18:18
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- pi_gate_simulated.jpg
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- 2014/10/25 18:49
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- rudolf.jpg
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- 2014/06/05 07:58
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- rupp.gif
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- single_gate.jpeg
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- 2014/10/25 18:49
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- single_gate_meshed.jpg
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- 2014/10/25 11:29
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- single_gate_simulated.jpg
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- 2014/10/25 18:50
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- tri_gate2.jpeg
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- 2014/10/25 18:50
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- tri_gate2.mp4
- 2014/09/17 07:56
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- 2014/10/25 18:51
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- tri_gate2_simulated.jpg
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- 2014/10/25 19:04
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- tri_gate3.jpeg
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- 2014/08/15 15:59
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- 2014/10/25 19:05
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- 2014/10/25 19:06
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- tri_gate4.jpeg
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- 2014/10/25 19:07
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- tri_gate4_me.jpg
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- 2014/12/02 00:59
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- tri_gate4_sim.jpg
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- 2014/12/02 00:59
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- tri_gate5.jpeg
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- 2014/08/15 15:59
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- tri_gate5.jpg
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- 2014/10/25 19:07
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- tri_gate5_me.jpg
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- 2014/12/02 00:59
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- tri_gate5_sim.jpg
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- 2014/12/02 00:57
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- viennamaterials_gui.png
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- 2015/03/06 12:16
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- viennamaterials_webui.png
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- 2015/03/06 12:16
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- viennastar_email.png
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- 2014/05/08 08:14
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- viennawd.png
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- 2015/03/06 12:16
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- virtualbox_acceleration.png
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- 2014/05/07 16:19
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- virtualbox_motherboard.png
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- 2014/05/07 16:19
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- virtualbox_processor.png
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- 2014/05/07 16:19
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- weinbub.jpg
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- 2014/06/05 07:58
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![[root]](/iuesoc/doku.php?id=2015-viennacl-openmp&ns=&tab_files=files&do=media&tab_details=view&image=double_gate_with_asymmetric_oxide_thickness.jpeg){kind=link}
File
- Title:
- Double_Gate_MOSFET_asymmetric
- Date:
- 2014/10/25 18:31
- Filename:
- double_gate_with_asymmetric_oxide_thickness.jpeg
- Format:
- JPEG
- Size:
- 88KB
- Width:
- 640
- Height:
- 440
2015-viennacl-openmp.txt · Last modified: 2015/03/24 20:40 by viennastar
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