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cad_models [2014/10/25 18:55]
resutik [MOSFET and Single-Gate]
cad_models [2014/12/02 01:09]
resutik
Line 33: Line 33:
 **Type:** **Double-Gate FinFET** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 40 nm, **H<​sub>​FIN</​sub>​** 50 nm and **L<​sub>​G</​sub>​** 60 nm\\  **Type:** **Double-Gate FinFET** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 40 nm, **H<​sub>​FIN</​sub>​** 50 nm and **L<​sub>​G</​sub>​** 60 nm\\ 
 **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]] **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]]
 +{{:​double_gate_finfet_me.jpg?​direct&​200 |Double_Gate_FinFET_meshed}}\\
 +{{:​double_gate_finfet_sim.jpg?​direct&​200 |Double_Gate_FinFET_simulated}}\\
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
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 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 {{:​double_gate_finfet2_meshed.jpg?​200 |Double_Gate_FinFET2_meshed}}\\ {{:​double_gate_finfet2_meshed.jpg?​200 |Double_Gate_FinFET2_meshed}}\\
-{{:​double_gate_finfet2_simulated.jpg?​200 |Double_Gate_FinFET2_simulated_without_contacts}}\\ +{{:​double_gate_finfet2_simulated.jpg?​200 |Double_Gate_FinFET2_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
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 **Source:** [[http://​www.nextnano.de/​nextnano3/​tutorial/​2Dtutorial_DGMOS_5nm.htm|Double-Gate MOSFET]] **Source:** [[http://​www.nextnano.de/​nextnano3/​tutorial/​2Dtutorial_DGMOS_5nm.htm|Double-Gate MOSFET]]
 {{:​double_gate_mosfet_meshed.jpg?​200 |Double_Gate_MOSFET_meshed}}\\ ​ {{:​double_gate_mosfet_meshed.jpg?​200 |Double_Gate_MOSFET_meshed}}\\ ​
-{{:​double_gate_mosfet_simulated.jpg?​200 |Double_Gate_MOSFET_simulated_without_contacts}}\\ +{{:​double_gate_mosfet_simulated.jpg?​200 |Double_Gate_MOSFET_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 53: Line 55:
 **Source:** [[http://​www.nextnano.com/​nextnano3/​tutorial/​2Dtutorial1.htm|Double-Gate MOSFET]] **Source:** [[http://​www.nextnano.com/​nextnano3/​tutorial/​2Dtutorial1.htm|Double-Gate MOSFET]]
 {{:​double_gate_mosfet2_meshed.jpg?​200 |Double_Gate_MOSFET2_meshed}}\\ ​ {{:​double_gate_mosfet2_meshed.jpg?​200 |Double_Gate_MOSFET2_meshed}}\\ ​
-{{:​double_gate_mosfet2_simulated.jpg?​200 |Double_Gate_MOSFET2_simulated_without_contacts}}\\ +{{:​double_gate_mosfet2_simulated.jpg?​200 |Double_Gate_MOSFET2_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 60: Line 62:
 **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]] **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]]
 {{:​double_gate_mosfet3_meshed.jpg?​200 |Double_Gate_MOSFET3_meshed}}\\ ​ {{:​double_gate_mosfet3_meshed.jpg?​200 |Double_Gate_MOSFET3_meshed}}\\ ​
-{{:​double_gate_mosfet3_simulated.jpg?​200 |Double_Gate_MOSFET3_simulated_without_contacts}}\\ +{{:​double_gate_mosfet3_simulated.jpg?​200 |Double_Gate_MOSFET3_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 66: Line 68:
 **Type:** **Double-Gate with asymmetric oxide thickness** with **T<​sub>​OX-Top</​sub>​** 2 nm, **T<​sub>​OX-Bottom</​sub>​** 3 nm and **L<​sub>​G</​sub>​** 20 nm \\  **Type:** **Double-Gate with asymmetric oxide thickness** with **T<​sub>​OX-Top</​sub>​** 2 nm, **T<​sub>​OX-Bottom</​sub>​** 3 nm and **L<​sub>​G</​sub>​** 20 nm \\ 
 **Source:** [[http://​online.sfsu.edu/​mahmoodi/​papers/​paper_C38.pdf|Double-Gate SOI Devices]] **Source:** [[http://​online.sfsu.edu/​mahmoodi/​papers/​paper_C38.pdf|Double-Gate SOI Devices]]
-{{:​double_gate_mosfet_with_asymmetrick_oxide_thickness_meshed.jpg?​200 |Double_Gate_MOSFET_with_asymmetric_oxide_thickness_meshed}}\\  +{{:​double_gate_mosfet_with_asymmetrick_oxide_thickness_meshed.jpg?​200 |Double_Gate_MOSFET_asymmetric_meshed}}\\  
-{{:​double_gate_mosfet_with_asymmetric_oxide_thickness_simulated.jpg?​200 |Double_Gate_MOSFET_with_asymmetric_oxide_thickness_simulated_without_contacts}}\\ +{{:​double_gate_mosfet_with_asymmetric_oxide_thickness_simulated.jpg?​200 |Double_Gate_MOSFET_asymmetric_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 79: Line 81:
 **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]] **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]]
 {{:​tri_gate2_meshed.jpg?​200 |Tri_Gate2_meshed}}\\ ​ {{:​tri_gate2_meshed.jpg?​200 |Tri_Gate2_meshed}}\\ ​
-{{:​tri_gate2_simulated.jpg?​200 |Tri_Gate2_simulated_without_contacts}}\\ +{{:​tri_gate2_simulated.jpg?​200 |Tri_Gate2_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 86: Line 88:
 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 {{:​tri_gate3_meshed.jpg?​200 |Tri_Gate3_meshed}}\\ ​ {{:​tri_gate3_meshed.jpg?​200 |Tri_Gate3_meshed}}\\ ​
-{{:​tri_gate3_simulated.jpg?​200 |Tri_Gate3_simulated_without_contacts}}\\ +{{:​tri_gate3_simulated.jpg?​200 |Tri_Gate3_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
-{{:​tri_gate4.jpeg?​200 |}}+{{:​tri_gate4.jpeg?​200 |Tri_Gate4}}
 **Type:** **Tri-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 71,4 nm, **H<​sub>​FIN</​sub>​** 41,7 nm and **L<​sub>​G</​sub>​** 60 nm\\  **Type:** **Tri-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 71,4 nm, **H<​sub>​FIN</​sub>​** 41,7 nm and **L<​sub>​G</​sub>​** 60 nm\\ 
 **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]] **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]]
 +{{:​tri_gate4_me.jpg?​direct&​200 |Tri_Gate4_meshed}}\\
 +{{:​tri_gate4_sim.jpg?​direct&​200 |Tri_Gate4_simulated}}\\
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
-{{:​tri_gate5.jpg?​200 |}}+{{:​tri_gate5.jpg?​200 |Tri_Gate5}}
 **Type:** **Tri-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 55 nm, **H<​sub>​FIN</​sub>​** 36 nm and **L<​sub>​G</​sub>​** 60 nm\\  **Type:** **Tri-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 55 nm, **H<​sub>​FIN</​sub>​** 36 nm and **L<​sub>​G</​sub>​** 60 nm\\ 
 **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]] **Source:** [[http://​internationalsematech.org/​meetings/​archives/​reliability/​20021028/​09_Chau_Depleted_Substrate.pdf|Advanced Depleted-Substrate Transistors]]
 +{{:​tri_gate5_me.jpg?​direct&​200 |Tri_Gate5_meshed}}\\
 +{{:​tri_gate5_sim.jpg?​direct&​200 |Tri_Gate5_simulated}}\\
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 103: Line 109:
 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 {{:​bulk_tri_gate_meshed.jpg?​200 |Bulk_Tri_Gate_meshed}}\\ ​ {{:​bulk_tri_gate_meshed.jpg?​200 |Bulk_Tri_Gate_meshed}}\\ ​
-{{:​bulk_tri_gate_simulated.jpg?​200 |Bulk_Tri_Gate_simulated_without_contacts}}\\ +{{:​bulk_tri_gate_simulated.jpg?​200 |Bulk_Tri_Gate_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
-{{:​bulk_tri_gate2.jpeg?​200 |}}+{{:​bulk_tri_gate2.jpeg?​200 |Bulk_Tri_Gate2}}
 **Type:** **Bulk Tri-Gate** with **T<​sub>​OX</​sub>​** 0.85 nm, **W<​sub>​FIN</​sub>​** 8 nm, **Tapering Angle** of 84° and **L<​sub>​G</​sub>​** 24 nm\\  **Type:** **Bulk Tri-Gate** with **T<​sub>​OX</​sub>​** 0.85 nm, **W<​sub>​FIN</​sub>​** 8 nm, **Tapering Angle** of 84° and **L<​sub>​G</​sub>​** 24 nm\\ 
 **Source:** [[http://​ieeexplore.ieee.org/​stamp/​stamp.jsp?​tp=&​arnumber=6585747|Impact of Transistor Architecture]] **Source:** [[http://​ieeexplore.ieee.org/​stamp/​stamp.jsp?​tp=&​arnumber=6585747|Impact of Transistor Architecture]]
 +{{:​bulk_tri_gate2_me.jpg?​direct&​200 |Bulk_Tri_Gate2_meshed}}\\
 +{{:​bulk_tri_gate2_sim.jpg?​direct&​200 |Bulk_Tri_Gate2_simulated}}
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
Line 116: Line 124:
  that the gate material surrounds the channel region on all sides.  that the gate material surrounds the channel region on all sides.
  
-{{:​all_around_gate.jpeg?​200 |}}  ​+{{:​all_around_gate.jpeg?​200 |All_Around_Gate}}  ​
 **Type:** **All-Around-Gate** with **T<​sub>​OX</​sub>​** 1 nm and **L<​sub>​G</​sub>​** 5,6 nm\\ **Type:** **All-Around-Gate** with **T<​sub>​OX</​sub>​** 1 nm and **L<​sub>​G</​sub>​** 5,6 nm\\
 **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]] **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]]
 \\ \\ \\ \\ \\ \\  ​ \\ \\ \\ \\ \\ \\  ​
  
-{{:​all_around_gate2.jpeg?​200 |}}+{{:​all_around_gate2.jpeg?​200 |All_Around_Gate2}}
 **Type:** **All-Around-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 12 nm, **H<​sub>​FIN</​sub>​** 15 nm and **L<​sub>​G</​sub>​** 22 nm \\  **Type:** **All-Around-Gate** with **T<​sub>​OX</​sub>​** 1,2 nm, **W<​sub>​FIN</​sub>​** 12 nm, **H<​sub>​FIN</​sub>​** 15 nm and **L<​sub>​G</​sub>​** 22 nm \\ 
 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 +{{:​all_around_gate2.jpg?​direct&​200 |All_Around_Gate2_meshed}}\\
 +{{:​all_around_gate2_simul_me.jpg?​direct&​200 |All_Around_Gate2_simulated}}\\
 \\ \\ \\ \\ \\ \\  \\ \\ \\ \\ \\ \\ 
  
Line 130: Line 140:
 **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]] **Source:** [[http://​www.silvaco.com/​tech_lib_TCAD/​simulationstandard/​2006/​may/​a2/​a2.html|Nano Devices (SILVACO)]]
 {{:​four_gate4.jpg?​200 | Four_Gate_meshed}}\\ ​ {{:​four_gate4.jpg?​200 | Four_Gate_meshed}}\\ ​
-{{:​four_gate_sim_without_contacts.jpg?​200 |Four_Gate_simulated_without_contacts ​}}+{{:​four_gate_sim_without_contacts.jpg?​200 |Four_Gate_simulated}}
 \\ \\ \\ \\ \\ \\  \\ \\ \\ \\ \\ \\ 
  
Line 137: Line 147:
 FlexFET is a SOI IDG-CMOS technology with a damascene metal top gate\\ ​ FlexFET is a SOI IDG-CMOS technology with a damascene metal top gate\\ ​
 and an implanted JFET bottom gate that are self-aligned in a gate trench.\\ \\  and an implanted JFET bottom gate that are self-aligned in a gate trench.\\ \\ 
-{{:​flexfet.jpeg?​200 |}}+{{:​flexfet.jpeg?​200 |FlexFET}}
 **Type:** **FlexFET** with **T<​sub>​SI</​sub>​** 4 nm, **T<​sub>​OX</​sub>​** 11 nm and **L<​sub>​G</​sub>​** 32 nm\\  **Type:** **FlexFET** with **T<​sub>​SI</​sub>​** 4 nm, **T<​sub>​OX</​sub>​** 11 nm and **L<​sub>​G</​sub>​** 32 nm\\ 
 **Source:** [[http://​www.americansemi.com/​32nm_IDG_Flexfet_SOI_Transistor.pdf|Design of a 32nm Independently-Double-Gated FlexFET SOI Transistor]] **Source:** [[http://​www.americansemi.com/​32nm_IDG_Flexfet_SOI_Transistor.pdf|Design of a 32nm Independently-Double-Gated FlexFET SOI Transistor]]
Line 149: Line 159:
 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 {{:​omega_gate_meshed.jpg?​200 |Omega_Gate_meshed}}\\ ​ {{:​omega_gate_meshed.jpg?​200 |Omega_Gate_meshed}}\\ ​
-{{:​omega_gate_simulated.jpg?​200 |Omega_Gate_simulated_only_drain+channel+source}}\\ +{{:​omega_gate_simulated.jpg?​200 |Omega_Gate_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
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 **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]] **Source:** [[http://​www.nature.com/​nature/​journal/​v479/​n7373/​fig_tab/​nature10676_F5.html|Types of multigate MOSFET]]
 {{:​pi_gate_meshed.jpg?​200 |Pi_Gate_meshed}}\\ ​ {{:​pi_gate_meshed.jpg?​200 |Pi_Gate_meshed}}\\ ​
-{{:​pi_gate_simulated.jpg?​200 |Pi_Gate_simulated_only_drain+channel+source}}\\ +{{:​pi_gate_simulated.jpg?​200 |Pi_Gate_simulated}}\\ 
 \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\
  
cad_models.txt · Last modified: 2014/12/02 01:09 by resutik