4.5.2.2 DMOSFET Simulation

Fig. 4.24 to 4.25 show the forward biased characteristics of the DMOSFET for the temperatures of 300 K and 500 K. It has been stated in Chapter 3 that 4H-SiC is preferred over 6H-SiC for most electronics application because it has higher and more isotropic electron mobility than 6H-SiC. These simulation results demonstrate that the drain current in 4H-SiC is more than two fold compared to 6H-SiC for both temperature ranges.

Fig. 4.26 through Fig. 4.27 show the transfer characteristics of this structure for the temperatures of 300 K and 500 K.

Figure 4.24: On-state characteristics of DMOSFET at 300K for 6H-SiC (left), and 4H-SiC (right).

Figure 4.25: On-state characteristics of DMOSFET at 500K for 6H-SiC (left) and 4H-SiC (right).

The threshold voltage is V $_\mathrm{T}$=3.5V, as seen for both poltypes. For a gate voltage above threshold the on-state current and the transistor gain is larger at 300 K than at 500 K due to the decrease in carrier mobility with temperature. Many of the arguments mentioned for UMOSFET can be applied to VDMOSFET.

Figure 4.26: Transfer characteristics of DMOSFET at 300K for 6H-SiC (left), and 4H-SiC (right).

Figure 4.27: Transfer characteristics of DMOSFET at 500K for 6H-SiC (left), and 4H-SiC (right)

Figure 4.28: Influence of temperature on the transfer characteristics of DMOSFET in 6H-SiC (left) and 4H-SiC (right).

Figure 4.29: The electrons mobility profile at 300K (left) and 500K (right) for vertical DMOSFET in 4H-SiC.

Figure 4.30: Reverse voltage characteristics of 6H-SiC (left) and 4H-SiC (right) in vertical DMOSFET for different temperatures.

Here, in addition to the resistance of the MOS inversion layer, the specific resistance of the DMOSFET also includes the resistance of the JFET region between the implanted p-base regions, as a result the output current in DMOSFET, Fig. 4.28 (left) is significantly lower than UMOSFET, Fig. 4.20 (right). However, this drawback is overcompensated by using 4H-SiC DMOSFET as shown in Fig. 4.28 (right). The electrons mobility profile in 4H-SiC for two different temperatures is depicted in Fig. 4.29.

As the spacing between the base regions is increased to reduce the JFET resistance, the area of the device also increase, resulting larger $R_\mathrm{on,sp}$. In addition as the spacing increases, the effectiveness of the base regions in terminating the electric field in the blocking state degrades, increasing the filed in the oxide and lowering the blocking voltage. The optimum base spacing which is predicted by simulation produces a specific on-resistance of 46 m$\Omega$-cm$^{-3}$, FOM of 70 MW/cm$^{2}$.

Fig. 4.30 shows the reverse voltage characteristics of both 4H- and 6H-SiC vertical DMOSFETs. This device blocks 1800 V for 6H-SiC and slightly lower for 4H-SiC due to the lower electric field strength in 4H-SiC. However, the leakage current in 4H-SiC is slightly higher than that of 6H-SiC. A positive temperature coefficient is observed on the blocking characteristics of this device, nevertheless the leakage current is orders of magnitudes lower than in the UMOSFET. That is the advantage of the vertical DMOSFET when a higher blocking voltage operation is needed in addition to the removal of the trench problem by this geometry. T. Ayalew: SiC Semiconductor Devices Technology, Modeling, and Simulation