J. E. Lilienfeld, "Method and Apparatus for Controlling Electric Currents." U. S. Patent #1.745.175, 1930.

J. Bardeen and W. Brattain, "The Transistor, A Semiconductor Triode," Physical Review, vol. 74, no. 2, pp. 230-231, 1948.

J. Bardeen and W. Brattain, "Physical Principles Involved in Transistor Action," Physical Review, vol. 75, no. 8, pp. 1208-1226, 1949.

W. Shockley, M. Sparks, and G. K. Teal, "p-n Junction Transistors," Physical Review, vol. 83, no. 1, pp. 151-164, 1951.

D. Kahng and M. Atalla, "Silicon-Silicondioxide Field Induced Surface Devices," in Proc. IRE-AIEE Solid-State Device Res.Conf., 1960.

G. E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, no. 8, pp. 114-117, 1965.

G. E. Moore, "Lithography and the Future of Moore's Law," in Proc. Optical/Laser Microlithography VIII, vol. 2440, pp. 2-17, SPIE, 1995.

R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," IEEE J.Solid-State Circuits, vol. 9, no. 5, pp. 256-268, 1974.

H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, "Nanoscale CMOS," Proc.IEEE, vol. 87, no. 4, pp. 537-570, 1999.

G. Baccarani, M. Wordeman, and R. Dennard, "Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design," IEEE Trans.Electron Devices, vol. ED-31, no. 4, pp. 452-462, 1984.

"International Technology Roadmap for Semiconductors - 2001 Edition," 2001.

S. Thompson, M. Alavi, M. Hussein, P. Jacob, C. Kenyon, P. Moon, M. Prince, S. Sivakumar, S. Tyagi, and M. Bohr, "130nm Logic Technology Featuring 60nm Transistors, Low-K Dielectrics, and Cu Interconnects," Intel Technology Journal, vol. 6, no. 2, pp. 5-13, 2002.

B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kavalieros, A. Murthy, and R. Chau, "Transistor Elements for 30nm Physical Gate Lengths and Beyond," Intel Technology Journal, vol. 6, no. 2, pp. 42-54, 2002.

S. Thompson, P. Packan, and M. Bohr, "MOS Scaling: Transistor Challenges for the 21st Century," Intel Technology Journal, vol. 2, no. 3, pp. 1-19, 1998.

D. J. Frank and Y. Taur, "Design Considerations for CMOS Near the Limits of Scaling," Solid-State Electron., vol. 46, no. 3, pp. 315-320, 2002.

D. Vasileska, I. Knezevic, R. Akis, S. Ahmed, and D. K. Ferry, "The Role of Quantization Effects on the Operation of 50nm MOSFETs, 250nm FIBMOS Devices and Narrow-Width SOI Device Structures," Journal of Computational Electronics, vol. 1, no. 4, pp. 453-465, 2002.

B. Yu, C. H. J. Wann, E. D. Nowak, K. Noda, and C. Hu, "Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submironmeter MOSFETs," IEEE Trans.Electron Devices, vol. 44, no. 4, pp. 627-634, 1997.

F. Faggin and T. Klein, "Silicon Gate Technology," Solid-State Electron., vol. 13, no. 8, pp. 1125-1144, 1970.

K. F. Schuegraf and C. Hu, "Hole Injection $ SiO_2$ Breakdown Model for Very Low Voltage Lifetime Extrapolation," IEEE Trans.Electron Devices, vol. 41, no. 5, pp. 761-767, 1994.

P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable Work Function Molybdenum Gate Technology for FDSOI-CMOS," in Proc. Intl. Electron Devices Meeting, pp. 363-366, 2002.

D. A. Buchanan, "Scaling the Gate Dielectric: Materials, Integration and Reliability," IBM J.Res.Dev., vol. 43, no. 3, pp. 245-264, 1999.

C. M. Osburn, I. Kim, S. K. Han, I. De, K. F. Yee, S. Gannavaram, S. J. Lee, C.-H. Lee, Z. J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T. P. Ma, and M. C. Öztürk, "Vertically Scaled MOSFET Gate Stacks and Junctions: How Far are we Likely to Go?," IBM J.Res.Dev., vol. 46, no. 2/3, pp. 299-315, 2002.

K. A. Bowman, L. Wang, X. Tang, and J. D. Meindl, "A Circuit-Level Perspective of the Optimum Gate Oxide Thickness," IEEE Trans.Electron Devices, vol. 48, no. 8, pp. 1800-1810, 2001.

J. H. Stathis, "Reliability Limits for the Gate Insulator in CMOS Technology," IBM J.Res.Dev., vol. 46, no. 2/3, pp. 265-286, 2002.

H.-S. P. Wong, "Beyond the Conventional Transistor," IBM J.Res.Dev., vol. 46, no. 2/3, pp. 133-168, 2002.

A. Burenkov and J. Lorenz, "On the Role of Corner Effects in FinFETs," in Proc. 4th European Workshop on Ultimate Integration of Silicon, pp. 31-34, 2003.

A. Burenkov and J. Lorenz, "Corner Effect in Double and Triple Gate FinFETs," in Proc. European Solid-State Device Research Conf., pp. 135-138, 2003.

Y.-K. Choi, T.-J. King, and C. Hu, "Spacer FinFET: Nano-scale CMOS Technology for the Terabit Era," in Proc. Intl. Semiconductor Device Research Symposium, pp. 543-546, 2001.

K. Kim, C.-G. Hwang, and J. G. Lee, "DRAM Technology Perspective for Gigabit Era," IEEE Trans.Electron Devices, vol. 45, no. 3, pp. 598-608, 1998.

E. Bertagnolli, F. Hofmann, J. Willer, R. Maly, F. Lau, P. W. von Basse, M. Bollu, R. Thewes, U. Kollmer, U. Zimmermann, M. Hain, W. H. Krautschneider, A. Rusch, B. Hasler, A. Kohlhase, and H. Klose, "ROS: An Extremely High Density Mask ROM Technology Based on Vertical Transistor Cells," in Proc. Intl. Electron Devices Meeting, pp. 58-59, 1996.

B. Goebel, E. Bertagnolli, and F. Koch, "Reliability of Vertical MOSFETs for Gigascale Memory Applications," in Proc. Intl. Electron Devices Meeting, pp. 939-942, 1998.

T. Schulz, W. Rösner, L. Risch, A. Korbel, and U. Langmann, "Short-Channel Vertical Sidewall MOSFETs," IEEE Trans.Electron Devices, vol. 48, no. 8, pp. 1783-1788, 2001.

C. K. Date and J. D. Plummer, "Increased Hot-Carrier Effects Using SiGe Layers in Vertical Surrounding-Gate MOSFETs," IEEE Trans.Electron Devices, vol. 48, no. 12, pp. 2690-2694, 2001.

T. Schulz, W. Rösner, E. Landgraf, L. Risch, and U. Langmann, "Planar and Vertical Double Gate Concepts," Solid-State Electron., vol. 46, no. 7, pp. 985-989, 2002.

J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. D. Y. Li, and C. J. Radens, "Challenges and Future Directions for the Scaling of Dynamic Random-Access Memory (DRAM)," IBM J.Res.Dev., vol. 46, no. 2/3, pp. 187-212, 2002.

W. B. Choi, J. U. Chu, K. S. Jeong, E. Bae, and J.-W. Lee, "Ultrahigh-Density Nanotransistors by Using Selectively Grown Vertical Carbon Nanotubes," Appl.Phys.Lett., vol. 79, no. 26, pp. 3696-3698, 2001.

W. B. Choi, S. Chae, E. Bae, J.-W. Lee, B.-H. Cheong, J.-R. Kim, and J.-J. Kim, "Carbon-Nanotube-Based Nonvolatile Memory with Oxide-Nitride-Oxide Film and Nanoscale Channel," Appl.Phys.Lett., vol. 82, no. 2, pp. 275-277, 2003.

P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, "Carbon Nanotube Electronics," Proc.IEEE, vol. 91, no. 11, pp. 1772-1784, 2003.

N. Sano, A. Hiroki, and K. Matsuzawa, "Device Modeling and Simulations Toward Sub-10nm Semiconductor Devices," IEEE Trans. Nanotechnology, vol. 1, no. 1, pp. 63-71, 2002.

A. Schenk, "Physical Modeling of Deep-Submicron Devices," in Proc. European Solid-State Device Research Conf., pp. 9-16, 2001.

Z. Yu, R. W. Dutton, and R. A. Kiehl, "Circuit/Device Modeling at the Quantum Level," IEEE Trans.Electron Devices, vol. 47, no. 10, pp. 1819-1825, 2000.

Z. Yu, R. W. Dutton, and D. W. Yergeau, "Macroscopic Quantum Carrier Transport Modeling," in Proc. Simulation of Semiconductor Processes and Devices, pp. 1-9, 2001.

R. Stratton, "Diffusion of Hot and Cold Electrons in Semiconductor Barriers," Physical Review, vol. 126, no. 6, pp. 2002-2014, 1962.

K. Blotekjaer, "Transport Equations for Electrons in Two-Valley Semiconductors," IEEE Trans.Electron Devices, vol. 17, no. 1, pp. 38-47, 1970.

C. Y. Chang and S. M. Sze, ULSI Devices.
Wiley, 2000.

S. Selberherr, Analysis and Simulation of Semiconductor Devices.
Springer, 1984.

T. Grasser, T.-W. Tang, H. Kosina, and S. Selberherr, "A Review of Hydrodynamic and Energy-Transport Models for Semiconductor Device Simulation," Proc.IEEE, vol. 91, no. 2, pp. 251-274, 2003.

T. Grasser, H. Kosina, M. Gritsch, and S. Selberherr, "Using Six Moments of Boltzmann's Transport Equation for Device Simulation," J.Appl.Phys., vol. 90, no. 5, pp. 2389-2396, 2001.

W. Liang, N. Goldsman, I. Mayergoyz, and P. J. Oldiges, "2-D MOSFET Modeling Including Surface Effects and Impact Ionization by Self-Consistent Solution of the Boltzmann, Poisson, and Hole-Continuity Equations," IEEE Trans.Electron Devices, vol. 44, no. 2, pp. 257-267, 1997.

N. Goldsman, C.-K. Lin, Z. Han, and C.-K. Huang, "Advances in the Spherical Harmonic-Boltzmann-Wigner Approach to Device Simulation," Superlattices & Microstructures, vol. 27, no. 2/3, pp. 159-175, 2000.

Z. Han, C.-K. Lin, N. Goldsman, I. Mayergoyz, S. Yu, and M. Stettler, "Gate Leakage Current Simulation by Boltzmann Transport Equation and its Dependence on the Gate Oxide Thickness," in Proc. Simulation of Semiconductor Processes and Devices, pp. 247-250, 1999.

C.-K. Huang and N. Goldsman, "2-D Self-Consistent Solution of Schrödinger Equation, Boltzmann Transport Equation, Poisson and Current-Continuity Equations for MOSFET," in Proc. Simulation of Semiconductor Processes and Devices, pp. 148-151, 2001.

C.-K. Huang and N. Goldsman, "Non-Equilibrium Modeling of Tunneling Gate Currents in Nanoscale MOSFETs," Solid-State Electron., vol. 47, no. 4, pp. 713-720, 2003.

M. Gritsch, Numerical Modeling of Silicon-on-Insulator MOSFETs.
Dissertation, Technische Universität Wien, 2002.

C. Jacoboni and L. Reggiani, "The Monte Carlo Method for the Solution of Charge Transport in Semiconductors with Applications to Covalent Materials," Reviews of Modern Physics, vol. 55, no. 3, pp. 645-705, 1983.

M. V. Fischetti and S. E. Laux, "Monte Carlo Study of Electron Transport in Silicon Inversion Layers," Physical Review B, vol. 48, no. 4, pp. 2244-2274, 1993.

A. Abramo, L. Baudry, R. Brunetti, R. Castagne, M. Charef, F. Dessenne, P. Dollfus, R. Dutton, W. L. Engl, R. Fauquembergue, C. Fiegna, M. V. Fischetti, S. Galdin, N. Goldsman, M. Hackel, C. Hamaguchi, K. Hess, K. Hennacy, P. Hesto, J. M. Higman, T. Iizuka, C. Jungemann, Y. Kamakura, H. Kosina, T. Kunikiyo, S. E. Laux, H. Lin, C. Maziar, H. Mizuno, H. J. Peifer, S. Ramaswamy, N. Sano, P. G. Scrobohaci, S. Selberherr, M. Takenaka, T.-W. Tang, K. Taniguchi, J. L. Thobel, R. Thoma, K. Tomizawa, M. Tomizawa, T. Vogelsang, S.-L. Wang, X. Wang, C.-S. Yao, P. D. Yoder, and A. Yoshii, "A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon," IEEE Trans.Electron Devices, vol. 41, no. 9, pp. 1646-1654, 1994.

S. E. Laux, M. V. Fischetti, and D. J. Frank, "Monte Carlo Analysis of Semiconductor Devices: The DAMOCLES Program," IBM J.Res.Dev., vol. 34, no. 4, pp. 466-494, 1990.

S. E. Laux and M. V. Fischetti, "Transport Models for Advanced Device Simulation - Truth or Consequences?," in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, pp. 27-34, 1995.

J. D. Bude and M. Mastrapasqua, "Impact Ionization and Distribution Functions in Sub-Micron nMOSFET Technologies," IEEE Electron Device Lett., vol. 16, no. 10, pp. 439-441, 1995.

A. Duncan, U. Ravaioli, and J. Jakumeit, "Full-Band Monte Carlo Investigation of Hot Carrier Trends in the Scaling of Metal-Oxide-Semiconductor Field-Effect Transistors," IEEE Trans.Electron Devices, vol. 45, no. 4, pp. 867-876, 1998.

C. Jungemann and B. Meinerzhagen, Hierarchical Device Simulation. The Monte Carlo Perspective.
Springer, 2003.

E. Schrödinger, "Quantisierung als Eigenwertproblem," Annalen der Physik, vol. 79, pp. 361-376, 1926.

R. Kassing, Physikalische Grundlagen der elektronischen Halbleiterbauelemente.
AULA, 1997.

A. Pacelli, "Self-Consistent Solution of the Schrödinger Equation in Semiconductor Devices by Implicit Iteration," IEEE Trans.Electron Devices, vol. 44, no. 7, pp. 1169-1171, 1997.

A. Pacelli, On the Modeling of Quantization and Hot Carrier Effects in Scaled MOSFETs and Other Modern Devices.
Dissertation, Polytechnic Institute of Milan, 1997.

E. Wigner, "On the Quantum Correction for Thermodynamic Equilibrium," Physical Review, vol. 40, pp. 749-759, 1932.

K. L. Jensen and A. K. Ganguly, "Simulation of Quantum Tunneling: Transmission Coefficient vs. Wigner Function Approaches," in Proc. NASECODE VIII, pp. 44-45, 1992.

K. L. Jensen and A. K. Ganguly, "Numerical Simulation of Field Emission and Tunneling: A Comparison of the Wigner Function and Transmission Coefficient Approaches," J.Appl.Phys., vol. 73, no. 9, pp. 4409-4427, 1993.

M. G. Ancona and H. F. Tiersten, "Quantum Correction to the Equation of State of an Electron Gas in a Semiconductor," Physical Review B, vol. 39, no. 13, pp. 9536 - 9540, 1989.

M. G. Ancona, "Macroscopic Description of Quantum-Mechanical Tunneling," Physical Review B, vol. 42, no. 2, pp. 1222 - 1233, 1990.

M. G. Ancona, Z. Yu, R. W. Dutton, P. J. V. Voorde, M. Cao, and D. Vook, "Density-Gradient Analysis of Tunneling in MOS Structures with Ultra-Thin Oxides," in Proc. Simulation of Semiconductor Processes and Devices, pp. 235-238, 1999.

M. G. Ancona, Z. Yu, R. W. Dutton, P. J. V. Voorde, M. Cao, and D. Vook, "Density-Gradient Analysis of MOS Tunneling," IEEE Trans.Electron Devices, vol. 47, no. 12, pp. 2310-2319, 2000.

M. G. Ancona and B. A. Biegel, "Nonlinear Discretization Scheme for the Density-Gradient Equations," in Proc. Simulation of Semiconductor Processes and Devices, pp. 196-199, 2000.

M. G. Ancona, "Equations of State for Silicon Inversion Layers," IEEE Trans.Electron Devices, vol. 47, no. 7, pp. 1449-1456, 2000.

C. L. Gardner, "The Classical and Quantum Hydrodynamic Models," in Proc. Intl. Workshop on Computational Electronics, pp. 25-36, 1993.

T. Hoehr, A. Schenk, A. Wettstein, and W. Fichtner, "On Density-Gradient Modeling of Tunneling Through Insulators," in Proc. Simulation of Semiconductor Processes and Devices, pp. 275-278, 2002.

A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, "Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study," IEEE Trans.Electron Devices, vol. 48, no. 4, pp. 722-729, 2001.

A. Asenov, A. R. Brown, and J. R. Watling, "Quantum Corrections in the Simulation of Decanano MOSFETs," Solid-State Electron., vol. 47, no. 7, pp. 1141-1145, 2003.

A. R. Brown, A. Asenov, and J. R. Watling, "Intrinsic Fluctuations in Sub 10nm Double-Gate MOSFETs Introduced by Discreteness of Charge and Matter," IEEE Trans. Nanotechnology, vol. 1, no. 4, pp. 195-200, 2002.

D. Connelly, Z. Yu, and D. Yergeau, "Macroscopic Simulation of Quantum Mechanical Effects in 2-D MOS Devices via the Density Gradient Method," IEEE Trans.Electron Devices, vol. 49, no. 2, pp. 619-626, 2002.

K. Matsuzawa, S.-I. Takagi, M. Takayanagi, and H. Tanimoto, "Device Simulation of Surface Quantization Effect on MOSFETs with Simplified Density-Gradient Method," Solid-State Electron., vol. 46, no. 5, pp. 747-751, 2002.

A. Wettstein, Quantum Effects in MOS Devices.
PhD thesis, ETH Zürich, 2000.

A. Wettstein, A. Schenk, and W. Fichtner, "Quantum Device-Simulation with the Density-Gradient Model on Unstructured Grids," IEEE Trans.Electron Devices, vol. 48, no. 2, pp. 279-284, 2001.

J.-R. Zhou and D. K. Ferry, "Simulation of Ultra-Small GaAs MESFET Using Quantum Moment Equations," IEEE Trans.Electron Devices, vol. 39, no. 3, pp. 473-478, 1992.

H. Tsuchiya and T. Miyoshi, "Quantum Transport Modeling of Ultrasmall Semiconductor Devices," IEICE Trans.Electron., vol. E82-C, no. 6, pp. 880-888, 1999.

L. Shifren, C. Ringhofer, and D. K. Ferry, "A Wigner Function-Based Quantum Ensemble Monte Carlo Study of a Resonant Tunneling Diode," IEEE Trans.Electron Devices, vol. 50, no. 3, pp. 769-773, 2003.

B. Winstead and U. Ravaioli, "A Quantum Correction Based on Schrödinger Equation Applied to Monte Carlo Device Simulation," IEEE Trans.Electron Devices, vol. 50, no. 2, pp. 440-446, 2003.

H. Kosina, M. Nedjalkov, and S. Selberherr, "A Monte Carlo Method Seamlessly Linking Quantum and Classical Transport Calculations," in Proc. Intl. Workshop on Computational Electronics, 2003.

Y. Li, T.-W. Tang, and X. Wang, "Modeling of Quantum Effects for Ultrathin Oxide MOS Structures with an Effective Potential," IEEE Trans. Nanotechnology, vol. 1, no. 4, pp. 238-242, 2002.

S. S. Ahmed and D. Vasileska, "Threshold Voltage Shifts in Narrow-Width SOI Devices Due to Quantum Mechanical Size-Quantization Effects," in Proc. Nanotech 2003 Vol. 2, pp. 222-225, 2003.

S. Datta, Electronic Transport in Mesoscopic Systems.
Cambridge University Press, 1995.

D. K. Ferry and S. M. Goodnick, Transport in Nanostructures.
Cambridge University Press, 1997.

S. Datta, "Nanoscale Device Modeling: the Green's Function Method," Superlattices & Microstructures, vol. 28, no. 4, pp. 253-278, 2000.

S. Datta, "The Non-Equilibrium Green's Function (NEGF) Formalism: An Elementary Introduction," in Proc. Intl. Electron Devices Meeting, pp. 29.1.1-29.1.4, 2002.

J. P. Shiely, Simulation of Tunneling in MOS Devices.
Dissertation, Duke University, 1999.

R. Clerc, Etude des Effets Quantiques dans les Composants CMOS a Oxydes de Grille Ultra Minces -- Modelisation et Caracterisation.
Dissertation, Institut National Polytechnique de Grenoble, 2001.

C. B. Duke, Tunneling in Solids.
Academic Press, 1969.

R. Tsu and L. Esaki, "Tunneling in a Finite Superlattice," Appl.Phys.Lett., vol. 22, no. 11, pp. 562-564, 1973.

N. Ashcroft and N. Mermin, Solid State Physics.
Harcourt College Publishers, 1976.

D. Cassi and B. Riccó, "An Analytical Model of the Energy Distribution of Hot Electrons," IEEE Trans.Electron Devices, vol. 37, no. 6, pp. 1514-1521, 1990.

A. Abramo and C. Fiegna, "Electron Energy Distributions in Silicon Structures at Low Applied Voltages and High Electric Fields," J.Appl.Phys., vol. 80, no. 2, pp. 889-893, 1996.

K.-I. Sonoda, M. Yamaji, K. Taniguchi, C. Hamaguchi, and S. T. Dunham, "Moment Expansion Approach to Calculate Impact Ionization Rate in Submicron Silicon Devices," J.Appl.Phys., vol. 80, no. 9, pp. 5444-5448, 1996.

C. Fiegna, F. Venturi, M. Melanotte, E. Sangiorgi, and B. Riccó, "Simple and Efficient Modeling of EPROM Writing," IEEE Trans.Electron Devices, vol. 38, no. 3, pp. 603-610, 1991.

K. Hasnat, C.-F. Yeap, S. Jallepalli, S. A. Hareland, W.-K. Shih, V. M. Agostinelli, A. F. Tasch, and C. M. Maziar, "Thermionic Emission Model of Electron Gate Current in Submicron NMOSFETs," IEEE Trans.Electron Devices, vol. 44, no. 1, pp. 129-138, 1997.

T. Grasser, H. Kosina, C. Heitzinger, and S. Selberherr, "Characterization of the Hot Electron Distribution Function Using Six Moments," J.Appl.Phys., vol. 91, no. 6, pp. 3869-3879, 2002.

T. Grasser, H. Kosina, and S. Selberherr, "Influence of the Distribution Function Shape and the Band Structure on Impact Ionization Modeling," J.Appl.Phys., vol. 90, no. 12, pp. 6165-6171, 2001.

E. Nicollian and J. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology.
Wiley, 1982.

Y. Tsividis, Operation and Modeling of the MOS Transistor.
McGraw-Hill, 1987.

S. M. Sze, Physics of Semiconductor Devices.
Wiley, second ed., 1981.

M. Levinshtein, S. Rumyantsev, and M. Shur, Handbook Series on Semiconductor Parameters, vol. 1.
World Scientific, 1996.

Y.-C. Yeo, T.-J. King, and C. Hu, "Metal-Dielectric Band Alignment and its Implications for Metal Gate Complementary Metal-Oxide-Semiconductor Technology," J.Appl.Phys., vol. 92, no. 12, pp. 7266-7271, 2002.

W. Harrison, Solid State Theory.
Dover, 1979.

W. Harrison, Electronic Structure and the Properties of Solids.
Dover Publications, 1989.

E. H. Rhoderick and R. H. Williams, Metal-Semiconductor Contacts.
Oxford Press, 1988.

W. Franz, Handbuch der Physik, vol. XVII, p. 155.
Springer, 1956.

M. V. Fischetti, S. E. Laux, and E. Crabbé, "Understanding Hot-Electron Transport in Silicon Devices: Is There a Shortcut?," J.Appl.Phys., vol. 78, no. 2, pp. 1058-1085, 1995.

M. Kleefstra and G. C. Herman, "Influence of the Image Force on the Band Gap in Semiconductors and Insulators," J.Appl.Phys., vol. 51, no. 9, pp. 4923-4926, 1980.

F. Jiménez-Molinos, F. Gámiz, A. Palma, P. Cartujo, and J. A. Lopez-Villanueva, "Direct and Trap-Assisted Elastic Tunneling Through Ultrathin Gate Oxides," J.Appl.Phys., vol. 91, no. 8, pp. 5116-5124, 2002.

G. Yang, K. Chin, and R. Marcus, "Electron Field Emission Through a Very Thin Oxide Layer," IEEE Trans.Electron Devices, vol. 38, no. 10, pp. 2373-2376, 1991.

A. Schenk and G. Heiser, "Modeling and Simulation of Tunneling through Ultra-Thin Gate Dielectrics," J.Appl.Phys., vol. 81, no. 12, pp. 7900-7908, 1997.

A. Schenk, Advanced Physical Models for Silicon Device Simulation.
Springer, 1998.

C. Fiegna, E. Sangiorgi, and L. Selmi, "Oxide-Field Dependence of Electron Injection from Silicon into Silicon Dioxide," IEEE Trans.Electron Devices, vol. 40, no. 11, pp. 2018-2022, 1993.

Z. A. Weinberg, "On Tunneling in Metal-Oxide Silicon Structures," J.Appl.Phys., vol. 53, no. 7, pp. 5052-5056, 1982.

W.-Y. Quan, D. M. Kim, and M. K. Cho, "Unified Compact Theory of Tunneling Gate Current in Metal-Oxide-Semiconductor Structures: Quantum and Image Force Barrier Lowering," J.Appl.Phys., vol. 92, no. 7, pp. 3724-3729, 2002.

L. Larcher, A. Paccagnella, and G. Ghidini, "Gate Current in Ultrathin MOS Capacitors: A New Model of Tunnel Current," IEEE Trans.Electron Devices, vol. 48, no. 2, pp. 271-278, 2001.

B. Majkusiak, "Gate Tunnel Current in an MOS Transistor," IEEE Trans.Electron Devices, vol. 37, no. 4, pp. 1087-1092, 1990.

A. Hadjadj, G. Salace, and C. Petit, "Fowler-Nordheim Conduction in Polysilicon (n+)-Oxide-Silicon(p) Structures: Limit of the Classical Treatment in the Barrier Height Determination," J.Appl.Phys., vol. 89, no. 12, pp. 7994-8001, 2001.

S. Nagano, M. Tsukiji, E. Hasegawa, and A. Ishitani, "Mechanism of Leakage Current Through the Nanoscale SiO2 Layer," J.Appl.Phys., vol. 75, no. 7, pp. 3530-3535, 1994.

A. Messiah, Quantenmechanik 1.
DeGruyter, 1991.

S. Gasiorowicz, Quantum Physics.
John Wiley & Sons, 1995.

L. F. Register, E. Rosenbaum, and K. Yang, "Analytic Model for Direct Tunneling Current in Polycristalline Silicon-Gate Metal-Oxide-Semiconductor Devices," Appl.Phys.Lett., vol. 74, no. 3, pp. 457-459, 1999.

H. Y. Yang, H. Niimi, and G. Lucovsky, "Tunneling Currents Through Ultrathin Oxide/Nitride Dual Layer Gate Dielectrics for Advanced Microelectronic Devices," J.Appl.Phys., vol. 83, no. 4, pp. 2327-2337, 1998.

N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, "Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance-Voltage Measurements in MOS Devices," IEEE Trans.Electron Devices, vol. 46, no. 7, pp. 1464-1471, 1999.

M. I. Vexler, N. Asli, A. F. Shulekin, B. Meinerzhagen, and P. Seegebrecht, "Compact Quantum Model for a Silicon MOS Tunnel Diode," Microelectronic Engineering, vol. 59, no. 1-4, pp. 161-166, 2001.

J. Zhang, J. S. Yuan, Y. Ma, and A. S. Oates, "Design Optimization of Stacked Layer Dielectrics for Minimum Gate Leakage Currents," Solid-State Electron., vol. 44, no. 12, pp. 2165-2170, 2000.

K. H. Gundlach, "Zur Berechnung des Tunnelstroms durch eine trapezförmige Potentialstufe," Solid-State Electron., vol. 9, pp. 949-957, 1966.

M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions.
Dover, 1972.

A. Shanware, J. P. Shiely, and H. Z. Massoud, "Extraction of the Gate Oxide Thickness of N- and P-Channel MOSFETs Below 20 Å from the Substrate Current Resulting from Valence-Band Electron Tunneling," in Proc. Intl. Electron Devices Meeting, pp. 815-818, 1999.

M. O. Vassell, J. Lee, and H. F. Lockwood, "Multibarrier Tunneling in Ga$ _{1-x}$Al$ _x$As/GaAs Heterostructures," J.Appl.Phys., vol. 54, no. 9, pp. 5208-5213, 1983.

Y. Ando and T. Itoh, "Calculation of Transmission Tunneling Current Across Arbitrary Potential Barriers," J.Appl.Phys., vol. 61, no. 4, pp. 1497-1502, 1987.

B. Zimmermann, E. Marclay, M. Ilegems, and P. Gueret, "Self-Consistent Calculations of Tunneling Currents in n+-GaAs/i-Al$ _x$Ga$ _{1-x}$As/n+-GaAs Structures and Comparison with Measurements," J.Appl.Phys., vol. 64, no. 7, pp. 3581-3588, 1988.

G. Yong, "Quantum Magnetotransport of Electrons in Double-Barrier Resonant-Tunneling Structures," Physical Review B, vol. 50, no. 23, pp. 17249-17255, 1994.

R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis, "Theory of Direct Tunneling Current in Metal-Oxide-Semiconductor Structures," J.Appl.Phys., vol. 91, no. 3, pp. 1400-1409, 2002.

W. W. Lui and M. Fukuma, "Exact Solution of the Schrödinger Equation Across an Arbitrary One-Dimensional Piecewise-Linear Potential Barrier," J.Appl.Phys., vol. 60, no. 5, pp. 1555-1559, 1986.

K. F. Brennan, "Self-Consistent Analysis of Resonant Tunneling in a Two-Barrier-One-Well Microstructure," J.Appl.Phys., vol. 62, no. 6, pp. 2392-2400, 1987.

D. C. Hutchings, "Transfer Matrix Approach to the Analysis of an Arbitrary Quantum Well Structure in an Electric Field," Appl.Phys.Lett., vol. 55, no. 11, pp. 1082-1084, 1989.

J.-G. S. Demers and R. Maciejko, "Propagation Matrix Formalism and Efficient Linear Potential Solution to Schrödinger's Equation," J.Appl.Phys., vol. 90, no. 12, pp. 6120-6129, 2001.

B. A. Biegel, Quantum Electronic Device Simulation.
Dissertation, Stanford University, 1997.

J. N. Schulman and Y.-C. Chang, "Reduced Hamiltonian Method for Solving the Tight-Binding Model of Interfaces," Physical Review B, vol. 27, no. 4, pp. 2346-2354, 1983.

D. Y. K. Ko and J. C. Inkson, "Matrix Method for Tunneling in Heterostructures: Resonant Tunneling in Multilayer Systems," Physical Review B, vol. 38, no. 14, pp. 9945-9951, 1988.

T. Usuki, M. Saito, M. Takatsu, R. A. Kiehl, and N. Yokoyama, "Numerical Analysis of Ballistic-Electron Transport in Magnetic Fields by Using a Quantum Point Contact and a Quantum Wire," Physical Review B, vol. 52, no. 11, pp. 8244-8258, 1995.

D. Z. Y. Ting, E. T. Yu, and T. C. McGill, "Multiband Treatment of Quantum Transport in Interband Tunnel Devices," Physical Review B, vol. 45, no. 7, pp. 3583-3592, 1992.

W. R. Frensley and N. G. Einspruch, eds., Heterostructures and Quantum Devices.
VLSI Electronics: Microstructure Science, Academic Press, 1994.

C. S. Lent and D. J. Kirkner, "The Quantum Transmitting Boundary Method," J.Appl.Phys., vol. 67, no. 10, pp. 6353-6359, 1990.

A. P. Gnädinger and H. E. Talley, "Quantum Mechanical Calculation of the Carrier Distribution and the Thickness of the Inversion Layer of a MOS Field-Effect Transistor," Solid-State Electron., vol. 13, no. 9, pp. 1301-1309, 1970.

F. Stern, "Self-Consistent Results for n-Type Si Inversion Layers," Physical Review B, vol. 5, no. 12, pp. 4891-4899, 1972.

W. Magnus and W. Schoenmaker, "On the Calculation of Gate Tunneling Currents in Ultra-Thin Metal-Insulator-Semiconductor Capacitors," Microelectronics Reliability, vol. 41, no. 1, pp. 31-35, 2001.

E. Anemogiannis, E. N. Glytsis, and T. K. Gaylord, "Bound and Quasibound State Calculation for Biased/Unbiased Semiconductor Heterostructures," IEEE J.Quantum Electronics, vol. 29, no. 11, pp. 2731-2740, 1993.

E. Cassan, "On the Reduction of Direct Tunneling Leakage through Ultrathin Gate Oxides by a One-Dimensional Schrödinger-Poisson Solver," J.Appl.Phys., vol. 87, no. 11, pp. 7931-7939, 2000.

A. T. M. Fairus and V. K. Arora, "Quantum Engineering of Nanoelectric Devices: the Role of Quantum Confinement on Mobility Degradation," Microelectronics Journal, vol. 32, no. 8, pp. 679-686, 2000.

N. Matsuo, Y. Takami, and Y. Kitagawa, "Modeling of Direct Tunneling for Thin SiO$ _2$ Film on n-Type Si (100) by WKB Method Considering the Quantum Effect in the Accumulation Layer," Solid-State Electron., vol. 46, no. 4, pp. 577-579, 2002.

S. Padmanabhan and A. Rothwarf, "Quantum Inversion Layer Mobility: Numerical Results," IEEE Trans.Electron Devices, vol. 36, no. 11, pp. 2557-2566, 1989.

M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A Simple Model for Quantisation Effects in Heavily-Doped Silicon MOSFETs at Inversion Conditions," Solid-State Electron., vol. 37, no. 3, pp. 411-414, 1994.

G. Gildenblatt, B. Gelmont, and S. Vatannia, "Resonant Behavior, Symmetry, and Singularity of the Transfer Matrix in Asymmetric Tunneling Structures," J.Appl.Phys., vol. 77, no. 12, pp. 6327-6331, 1995.

P. J. Price, "Resonant Tunneling via an Accumulation Layer," Physical Review B, vol. 45, no. 16, pp. 9042-9045, 1992.

P. J. Price, "Electron Tunneling from Channel to Gate," Appl.Phys.Lett., vol. 82, no. 13, pp. 2080-2081, 2003.

A. Thean and J. P. Leburton, "3-D Computer Simulation of Single-Electron Charging in Silicon Nanocrystal Floating Gate Flash Memory Devices," IEEE Electron Device Lett., vol. 22, no. 3, pp. 148-150, 2001.

A. Ghetti, A. Hamad, P. J. Silverman, H. Vaidya, and N. Zhao, "Self-Consistent Simulation of Quantization Effects and Tunneling Current in Ultra-Thin Gate Oxide MOS Devices," in Proc. Simulation of Semiconductor Processes and Devices, pp. 239-242, 1999.

S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs," IEEE Trans.Electron Devices, vol. 18, no. 5, pp. 209-211, 1997.

S. Mudanai, Y. Fan, Q. Ouyang, A. F. Tasch, and S. K. Banerjee, "Modeling of Direct Tunneling Current Through Gate Dielectric Stacks," IEEE Trans.Electron Devices, vol. 47, no. 10, pp. 1851-1857, 2000.

S. Mudanai, L. F. Register, A. F. Tasch, and S. K. Banerjee, "Understanding the Effects of Wave Function Penetration on the Inversion Layer Capacitance of NMOSFETs," IEEE Electron Device Lett., vol. 22, no. 3, pp. 145-147, 2001.

F. Rana, S. Tiwari, and D. A. Buchanan, "Self-Consistent Modeling of Accumulation Layers and Tunneling Currents Through Very Thin Oxides.," Appl.Phys.Lett., vol. 69, no. 8, pp. 1104-1106, 1996.

W.-K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar, and A. F. Tasch, jr., "Modeling Gate Leakage Current in nMOS Structures due to Tunneling through an Ultra-Thin Oxide," Solid-State Electron., vol. 42, no. 6, pp. 997-1006, 1998.

E. Cassan, P. Dollfus, S. Galdin, and P. Hesto, "Semiclassical and Wave-Mechanical Modeling of Charge Control and Direct Tunneling Leakage in MOS and H-MOS Devices with Ultrathin Oxides," IEEE Trans.Electron Devices, vol. 48, no. 4, pp. 715-721, 2001.

A. Dalla Serra, A. Abramo, P. Palestri, L. Selmi, and F. Widdershoven, "Closed- and Open-Boundary Models for Gate-Current Calculation in n-MOSFETs," IEEE Trans.Electron Devices, vol. 48, no. 8, pp. 1811-1815, 2001.

Z. Bai, J. Demmel, J. Dongarra, A. Ruhe, and H. van der Vorst, eds., Templates for the Solution of Algebraic Eigenvalue Problems: A Practical Guide.
SIAM, Philadelphia, 2000.

N. Arora, MOSFET Models for VLSI Circuit Simulation.
Springer, 1993.

C.-H. Choi, K.-H. Oh, J.-S. Goo, Z. Yu, and R. W. Dutton, "Direct Tunneling Current Model for Circuit Simulation," in Proc. Intl. Electron Devices Meeting, pp. 30.6.1-30.6.4, 1999.

C.-H. Choi, K.-Y. Nam, Z. Yu, and R. W. Dutton, "Impact of Gate Direct Tunneling Current on Circuit Performance: A Simulation Study," IEEE Trans.Electron Devices, vol. 48, no. 12, pp. 2823-2829, 2001.

Y.-S. Lin, H.-T. Huang, C.-C. Wu, Y.-K. Leung, H.-Y. Pan, T.-E. Chang, W.-M. Chen, J.-J. Liaw, and C. H. Diaz, "On the SiO$ _2$-Based Gate-Dielectric Scaling Limit for Low-Standby Power Applications in the Context of a 0.13$ \mu$m CMOS Logic Technology," IEEE Trans.Electron Devices, vol. 49, no. 3, pp. 442-448, 2002.

H. Lin, J. T.-Y. Chen, and J.-H. Chang, "Investigation of Disturbance for the New Dual Floating Gate Multilevel Flash Cells," Solid-State Electron., vol. 46, no. 8, pp. 1145-1150, 2002.

S. Schwantes and W. Krautschneider, "Relevance of Gate Current for the Functionality of Deep Submicron CMOS Circuits," in Proc. European Solid-State Device Research Conf., pp. 471-474, 2001.

R. H. Fowler and L. Nordheim, "Electron Emission in Intense Electric Fields," Proc.Roy.Soc.A, vol. 119, pp. 173-181, 1928.

M. Lenzlinger and E. H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown SiO$ _2$," J.Appl.Phys., vol. 40, no. 1, pp. 278-283, 1969.

K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-Thin Silicon Dioxide Leakage Current and Scaling Limit," in Proc. Symposium on VLSI Technology, pp. 18-19, 1992.

S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka, "Reliability Issues of Flash Memory Cells," Proc.IEEE, vol. 81, no. 5, pp. 776-788, 1993.

R. Moazzami and C. Hu, "Stress-Induced Current in Thin Silicon Dioxide Films," in Proc. Intl. Electron Devices Meeting, pp. 139-142, 1992.

E. Rosenbaum and L. F. Register, "Mechanism of Stress-Induced Leakage Current in MOS Capacitors," IEEE Trans.Electron Devices, vol. 44, no. 2, pp. 317-323, 1997.

S.-I. Takagi, N. Yasuda, and A. Toriumi, "A New I-V Model for Stress-Induced Leakage Current Including Inelastic Tunneling," IEEE J.Solid-State Circuits, vol. 46, no. 2, pp. 348-354, 1999.

R. Rofan and C. Hu, "Stress-Induced Oxide Leakage," IEEE Electron Device Lett., vol. 12, no. 11, pp. 632-634, 1991.

J. Wu, L. F. Register, and E. Rosenbaum, "Trap-Assisted Tunneling Current Through Ultra-Thin Oxide," in Proc. Intl. Reliability Physics Symposium, pp. 389-395, 1999.

B. Riccó, G. Gozzi, and M. Lanzoni, "Modeling and Simulation of Stress-Induced Leakage Current in Ultrathin SiO2 Films," IEEE Trans.Electron Devices, vol. 45, no. 7, pp. 1554-1560, 1998.

K. Sakakibara, N. Ajika, K. Eikyu, K. Ishikawa, and H. Miyoshi, "A Quantitative Analysis of Time-Decay Reproducible Stress-Induced Leakage Current in SiO2 Films," IEEE Trans.Electron Devices, vol. 44, no. 6, pp. 1002-1008, 1997.

A. Ghetti, E. Sangiorgi, J. Bude, T. W. Sorsch, and G. Weber, "Tunneling into Interface States as Reliability Monitor for Ultrathin Oxides," IEEE Trans.Electron Devices, vol. 47, no. 12, pp. 2358-2365, 2000.

C.-M. Yih, Z.-H. Ho, M.-S. Liang, and S. S. Chung, "Characterization of Hot-Hole Injection Induced SILC and Related Disturbs in Flash Memories," IEEE Trans.Electron Devices, vol. 48, no. 2, pp. 300-306, 2001.

A. I. Chou, K. Lai, K. Kumar, P. Chowdhury, and J. C. Lee, "Modeling of Stress-Induced Leakage Current in Ultrathin Oxides with the Trap-Assisted Tunneling Mechanism," Appl.Phys.Lett., vol. 70, no. 27, pp. 3407-3409, 1997.

K. Komiya and Y. Omura, "Spectroscopic Analysis of Stress-Induced Defects in Thin Silicon Oxide Films," Microelectronic Engineering, vol. 59, no. 1-4, pp. 61-65, 2001.

T.-K. Kang, M.-J. Chen, C.-H. Liu, Y. J. Chang, and S.-K. Fan, "Numerical Confirmation of Inelastic Trap-Assisted Tunneling (ITAT) as SILC Mechanism," IEEE Trans.Electron Devices, vol. 48, no. 10, pp. 2317-2322, 2001.

M. Lenski, T. Endoh, and F. Masuoka, "Analytical Modeling of Stress-Induced Leakage Currents in 5.1-9.6nm-thick silicon-dioxide films Based on Two-Step Inelastic Trap-Assisted Tunneling," J.Appl.Phys., vol. 88, no. 9, pp. 5238-5245, 2000.

S.-I. Takagi, N. Yasuda, and A. Toriumi, "Experimental Evidence of Inelastic Tunneling in Stress-Induced Leakage Current," IEEE Trans.Electron Devices, vol. 46, no. 2, pp. 335-341, 1999.

W. J. Chang, M. P. Houng, and Y. H. Wang, "Simulation of Stress-Induced Leakage Current in Silicon Dioxides: A Modified Trap-Assisted Tunneling Model considering Gaussian-Distributed Traps and Electron Energy Loss," J.Appl.Phys., vol. 89, no. 11, pp. 6285-6293, 2001.

W. J. Chang, M. P. Houng, and Y. H. Wang, "Electrical Properties and Modeling of Ultrathin Impurity-Doped Silicon Dioxides," J.Appl.Phys., vol. 90, no. 10, pp. 5171-5179, 2001.

L. Larcher, A. Paccagnella, and G. Ghidini, "A Model of the Stress Induced Leakage Current in Gate Oxides," IEEE Trans.Electron Devices, vol. 48, no. 2, pp. 285-288, 2001.

D. Ielmini, A. S. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC Based on Electron and Hole Tunneling - Part I: Transient Effects," IEEE Trans.Electron Devices, vol. 47, no. 6, pp. 1258-1265, 2000.

D. Ielmini, A. S. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC Based on Electron and Hole Tunneling - Part II: Steady-State," IEEE Trans.Electron Devices, vol. 47, no. 6, pp. 1266-1272, 2000.

D. Ielmini, A. S. Spinelli, A. L. Lacaita, A. Martinelli, and G. Ghidini, "A Recombination- and Trap-Assisted Tunneling Model for Stress-Induced Leakage Current," Solid-State Electron., vol. 45, no. 8, pp. 1361-1369, 2001.

D. Ielmini, A. S. Spinelli, A. L. Lacaita, and G. Ghidini, "Modeling of Stress-Induced Leakage Current and Impact Ionization in MOS Devices," Solid-State Electron., vol. 46, no. 3, pp. 417-422, 2002.

D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, "A New Two-Trap Tunneling Model for the Anomalous Stress-Induced Leakage Current (SILC) in Flash Memories," Microelectronic Engineering, vol. 59, no. 1-4, pp. 189-195, 2001.

D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, "Modeling of Anomalous SILC in Flash Memories Based on Tunneling at Multiple Defects," Solid-State Electron., vol. 46, no. 11, pp. 1749-1756, 2002.

A. Ghetti, "Characterization and Modeling of the Tunneling Current in Si-SiO$ _2$ - Si Structures with Ultra-Thin Oxide Layer," Microelectronic Engineering, vol. 59, no. 1-4, pp. 127-136, 2001.

C. Chaneliere, J. L. Autran, and R. A. B. Devine, "Conduction Mechanisms in Ta$ _2$O$ _5$/SiO$ _2$ and Ta$ _2$O$ _5$/Si$ _3$N$ _4$ Stacked Structures on Si," J.Appl.Phys., vol. 86, no. 1, pp. 480-486, 1999.

M. Houssa, R. Degraeve, P. W. Mertens, M. M. Heyns, J. S. Leon, A. Halliyal, and B. Ogle, "Electrical Properties of Thin SiON/Ta$ _2$O$ _5$ Gate Dielectric Stacks," J.Appl.Phys., vol. 86, no. 11, pp. 6462-6467, 1999.

M. Houssa, M. Tuominen, M. Naili, V. Afanas'ev, A. Stesmans, S. Haukka, and M. M. Heyns, "Trap-Assisted Tunneling in High Permittivity Gate Dielectric Stacks," J.Appl.Phys., vol. 87, no. 12, pp. 8615-8620, 2000.

D. Caputo, F. Irrera, S. Salerno, S. Spiga, and M. Fanciulli, "Reliability of ZrO$ _2$ Films Grown by Atomic Layer Deposition," in Proc. 4th European Workshop on Ultimate Integration of Silicon, pp. 89-92, 2003.

B. DeSalvo, G. Ghibaudo, G. Pananakakis, B. Guillaumot, and G. Reimbold, "A General Bulk-Limited Transport Analysis of a 10nm - thick Oxide Stress-Induced Leakage Current," Solid-State Electron., vol. 44, no. 6, pp. 895-903, 2000.

E. Kameda, T. Matsuda, Y. Emura, and T. Ohzone, "Fowler-Nordheim Tunneling in MOS Capacitors with Si-implanted SiO2," Solid-State Electron., vol. 42, no. 11, pp. 2105-2111, 1998.

J. A. López-Villanueva, J. A. Jiménez-Tejada, P. Cartujo, J. Bausells, and J. E. Carceller, "Analysis of the Effects of Constant-Current Fowler-Nordheim-Tunneling Injection with Charge Trapping Inside the Potential Barrier," J.Appl.Phys., vol. 70, no. 7, pp. 3712-3720, 1991.

F. Jiménez-Molinos, A. Palma, F. Gámiz, J. Banqueri, and J. A. Lopez-Villanueva, "Physical Model for Trap-Assisted Inelastic Tunneling in Metal-Oxide-Semiconductor Structures," J.Appl.Phys., vol. 90, no. 7, pp. 3396-3404, 2001.

A. Palma, A. Godoy, J. A. Jimenez-Tejada, J. E. Carceller, and J. A. Lopez-Villanueva, "Quantum Two-Dimensional Calculation of Time Constants of Random Telegraph Signals in Metal-Oxide-Semiconductor Structures," Physical Review B, vol. 56, no. 15, pp. 9565-9574, 1997.

J. H. Zheng, H. S. Tan, and S. C. Ng, "Theory of Non-Radiative Capture of Carriers by Multiphonon Processes for Deep Centres in Semiconductors," J.Phys.:Condensed Matter, vol. 6, no. 9, pp. 1695-1706, 1994.

W. B. Fowler, J. K. Rudra, M. E. Zvanut, and F. J. Feigl, "Hysteresis and Franck-Condon Relaxation in Insulator-Semiconductor Tunneling," Physical Review B, vol. 41, no. 12, pp. 8313-8317, 1990.

M. Herrmann and A. Schenk, "Field and High-Temperature Dependence of the Long Term Charge Loss in Erasable Programmable Read Only Memories: Measurements and Modeling," J.Appl.Phys., vol. 77, no. 9, pp. 4522-4540, 1995.

Institut für Mikroelektronik, Technische Universität Wien, Austria, MINIMOS-NT User's Guide, 2002.

Institut für Mikroelektronik, Technische Universität Wien, Austria, MINIMOS 6 User's Guide, 1994.

C. Fischer, Bauelementsimulation in einer computergestützten Entwurfsumgebung.
Dissertation, Technische Universität Wien, 1994.

T. Simlinger, Simulation von Heterostruktur-Feldeffekttransistoren.
Dissertation, Technische Universität Wien, 1996.

M. Knaipp, Modellierung von Temperatureinflüssen in Halbleiterbauelementen.
Dissertation, Technische Universität Wien, 1998.

T. Grasser, Mixed-Mode Device Simulation.
Dissertation, Technische Universität Wien, 1999.

V. Palankovski, Simulation of Heterojunction Bipolar Transistors.
Dissertation, Technische Universität Wien, 2000.

S. Wagner, The Minimos-NT Linear Equation Solving Module.
Diplomarbeit, Technische Universität Wien, 2001.

R. Klima, Three-Dimensional Device Simulation with MINIMOS-NT.
Dissertation, Technische Universität Wien, 2002.

S. Duvall, "An Interchange Format for Process and Device Simulation," IEEE Trans.Computer-Aided Design, vol. 7, no. 7, pp. 741-754, 1988.

T. Binder, Rigorous Integration of Semiconductor Process and Device Simulators.
Dissertation, Technische Universität Wien, 2002.

R. Entner, Three-Dimensional Device Simulation with MINIMOS-NT Using the Wafer-State-Server.
Diplomarbeit, Technische Universität Wien, 2003.

IBM, Open Visualization Data Explorer, 2002.

M. Zohlhuber, Visualisierung von Simulationsdaten.
Diplomarbeit, Technische Universität Wien, 2003.

R. B. Lehoucq and J. A. Scott, "An Evaluation of Software for Computing Eigenvalues of Sparse Nonsymmetric Matrices," Technical Report MCS-P547-1195, Argonne National Laboratory, Argonne, IL, 1996.

S. L. Moshier, "Cephes Mathematical Function Library," 1992.

H. T. Lau, A Numerical Library in C for Scientists and Engineers.
CRC Press, 1995.

R. Lake, G. Klimeck, R. C. Bowen, and D. Jovanovic, "Single and Multiband Modeling of Quantum Electron Transport Through Layered Semiconductor Devices," J.Appl.Phys., vol. 81, no. 12, pp. 7845-7869, 1997.

R. C. Bowen, W. R. Frensley, G. Klimeck, and R. K. Lake, "Transmission Resonances and Zeros in Multiband Models," Physical Review B, vol. 52, no. 4, pp. 2754-2765, 1995.

C. Bowen, C. L. Fernando, G. Klimeck, A. Chatterjee, D. Blanks, R. Lake, J. Hu, J. Davis, M. Kulkarni, S. Hattangady, and I.-C. Chen, "Physical Oxide-Thickness Extraction and Verification using Quantum Mechanical Simulation," in Proc. Intl. Electron Devices Meeting, pp. 35.1.1-35.1.4, 1997.

G. Klimeck, R. Lake, C. Bowen, W. R. Frensley, and T. S. Moise, "Quantum Device Simulation with a Generalized Tunneling Formula," Appl.Phys.Lett., vol. 67, no. 17, pp. 2539-2541, 1995.

C. L. Fernando and W. R. Frensley, "An Efficient Method for the Numerical Evaluation of Resonant States," J.Appl.Phys., vol. 76, no. 5, pp. 2881-2886, 1994.

W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C.
Cambridge University Press, 1997.

W. R. Frensley, "Numerical Evaluation of Resonant States," Superlattices & Microstructures, vol. 11, no. 3, pp. 347-350, 1992.

Raytheon TI Systems, Nanotechnology Engineering Modeling Program (NEMO) Version 3.0, 1996.

J. Cai and C.-T. Sah, "Gate Tunneling Currents in Ultrathin Oxide Metal-Oxide-Silicon Transistors," J.Appl.Phys., vol. 89, no. 4, pp. 2272-2285, 2001.

H. Z. Massoud and J. P. Shiely, "The Role of Substrate Carrier Generation in Determining the Electric Field in the Oxide of MOS Capacitors Biased in the Fowler-Nordheim Tunneling Regime," Microelectronic Engineering, vol. 36, no. 1, pp. 263-266, 1997.

Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFETS," IEEE Trans.Electron Devices, vol. 45, no. 11, pp. 2355-2360, 1998.

M. Städele, B. Tuttle, B. Fischer, and K. Hess, "Tunneling Through Thin Oxides - New Insights from Microscopic Calculations," Journal of Computational Electronics, vol. 1, pp. 153-159, 2002.

M. Städele, F. Sacconi, A. D. Carlo, and P. Lugli, "Enhancement of the Effective Tunnel Mass in Ultrathin Silicon Dioxide Layers," J.Appl.Phys., vol. 93, no. 5, pp. 2681-2690, 2003.

F. Sacconi, M. Povolotskyi, A. D. Carlo, P. Lugli, and M. Städele, "Full-Band Approaches to the Electronic Properties of Nanometer-Scale MOS Structures," in Proc. 4th European Workshop on Ultimate Integration of Silicon, pp. 125-128, 2003.

S. H. Lo, D. A. Buchanan, and Y. Taur, "Modeling and Characterization of Quantization, Polysilicon Depletion and Direct Tunneling Effects in MOSFETs with Ultrathin Oxides," IBM J.Res.Dev., vol. 43, no. 3, pp. 327-337, 1999.

S. Jallepalli, J. Bude, W.-K. Shih, M. R. Pinto, C. M. Maziar, and A. F. Tasch, jr., "Electron and Hole Quantization and Their Impact on Deep Submicron Silicon p- and n-MOSFET Characteristics," IEEE Trans.Electron Devices, vol. 44, no. 2, pp. 297-303, 1997.

Synopsys, MEDICI User's Manual, 2003.

L. Selmi, A. Ghetti, R. Bez, and E. Sangiorgi, "Trade-offs between Tunneling and Hot-Carrier Injection in Short Channel Floating Gate MOSFETs," Microelectronic Engineering, vol. 36, no. 1-4, pp. 293-296, 1997.

E. M. Vogel, K. Z. Ahmed, B. Hornung, K. Henson, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. J. Wortman, "Modeled Tunnel Currents for High Dielectric Constant Dielectrics," IEEE Trans.Electron Devices, vol. 45, no. 6, pp. 1350-1355, 1998.

M. LeRoy, E. Lheurette, O. Vanbesien, and D. Lippens, "Wave-Mechanical Calculations of Leakage Current Through Stacked Dielectrics for nanotransistor Metal-Oxide-Semiconductor Design," J.Appl.Phys., vol. 93, no. 5, pp. 2966-2971, 2003.

J. D. Casperson, L. D. Bell, and H. A. Atwater, "Materials Issues for Layered Tunnel Barrier Structures," J.Appl.Phys., vol. 92, no. 1, pp. 261-267, 2002.

G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k Gate Dielectrics: Current Status and Materials Properties Considerations," J.Appl.Phys., vol. 89, no. 10, pp. 5243-5275, 2001.

J. Robertson, "Band Offsets of Wide-Bandgap Oxides and Implications for Future Electronic Devices," J.Vac.Sci.Technol., vol. 18, no. 3, pp. 1785-1791, 2000.

Y.-Y. Fan, R. E. Nieh, J. C. Lee, G. Lucovsky, G. A. Brown, L. F. Register, and S. K. Banerjee, "Voltage- and Temperature-Dependent Gate Capacitance and Current Model: Application to ZrO$ _2$ n-Channel MOS Capacitor," IEEE Trans.Electron Devices, vol. 49, no. 11, pp. 1969-1978, 2002.

S. Harasek, Zirkoniumdioxiddünnfilme als hoch-$ \epsilon$ Gateisolatoren für die Siliziumtechnologie.
Dissertation, Technische Universität Wien, 2003.

P. Tanner, S. Dimitrijev, and H. B. Harrison, "Technique for Monitoring Slow Interface Trap Characteristics in MOS Capacitors," Electron.Lett., vol. 31, no. 21, pp. 1880-1881, 1995.

D. A. Antoniadis, I. J. Djomehri, K. M. Jackson, and S. Miller, ""Well-Tempered" Bulk-Si NMOSFET Device Home Page."

W. D. Brown and J. Brewer, Nonvolatile Semiconductor Memory Technology.
IEEE Press, 1998.

A. Concannon, S. Keeney, A. Mathewson, R. Bez, and C. Lombardi, "Two-Dimensional Numerical Analysis of Floating-Gate EEPROM Devices," IEEE Trans.Electron Devices, vol. 40, no. 7, pp. 1258-1262, 1993.

S. Keeney, R. Bez, D. Cantarelli, F. Piccinin, A. Mathewson, L. Ravazzi, and C. Lombardi, "Complete Transient Simulation of Flash EEPROM Devices," IEEE Trans.Electron Devices, vol. 39, no. 12, pp. 2750-2757, 1992.

A. Kolodny, S. T. K. Nieh, B. Eitan, and J. Shappir, "Analysis and Modeling of Floating-Gate EEPROM Cells," IEEE Trans.Electron Devices, vol. 33, no. 6, pp. 835-844, 1986.

K. T. San, C. Kaya, D. K. Y. Liu, T.-P. Ma, and P. Shah, "A New Technique for Determining the Capacitive Coupling Coefficients in Flash EPROM's," IEEE Electron Device Lett., vol. 13, no. 6, pp. 328-331, 1992.

R. Bouchakour, N. Harabech, P. Canet, P. Boivin, and J. M. Mirabel, "Modeling of a Floating-Gate EEPROM Cell Using a Charge Sheet Approach Including Variable Tunneling Capacitance Gate Depletion Effect," in Proc. Intl. Symposium on Circuits & Systems, pp. 822-825, 2001.

R. Duane, A. Concannon, P. O'Sullivan, M. O'Shea, and A. Mathewson, "Extraction of Coupling Ratios for Fowler-Nordheim Programming Conditions," Solid-State Electron., vol. 45, no. 2-3, pp. 235-242, 2001.

D. Kahng and S. M. Sze, "A Floating Gate and Its Application to Memory Devices," Bell Syst.Tech.J., vol. 46, no. 4, pp. 1288-1295, 1967.

P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash Memory Cells - An Overview," Proc.IEEE, vol. 86, no. 8, pp. 1248-1271, 1997.

P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories.
Kluwer Academic Publishers, 2000.

P. Canet, R. Bouchakour, N. Harabech, P. Boivin, J. M. Mirabel, and C. Plossu, "Study of Signal Programming to Improve EEPROM Cell Reliability," in Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, pp. 1144-1147, 2000.

M. K. Cho and D. M. Kim, "High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology," IEEE Electron Device Lett., vol. 21, no. 8, pp. 399-401, 2000.

J. M. Caywood, C. J. Huang, and Y. J. Chang, "A Novel Nonvolatile Memory Cell Suitable for Both Flash and Byte-Writable Applications," IEEE Trans.Electron Devices, vol. 49, no. 5, pp. 802-807, 2002.

B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, 2000.

M. H. White, D. A. Adams, and J. Bu, "On the Go with SONOS," IEEE Circuits & Devices, no. 7, pp. 22-31, 2000.

K.-T. Chang, W.-M. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K.-M. Chang, "A New SONOS Memory Using Source-Side Injection for Programming," IEEE Electron Device Lett., vol. 19, no. 7, pp. 253-255, 1998.

G. Iannaccone and P. Coli, "Three-Dimensional Simulation of Nanocrystal Flash Memories," Appl.Phys.Lett., vol. 78, no. 14, pp. 2046-2048, 2001.

A. Thean and J. P. Leburton, "Three-Dimensional Self-Consistent Simulation of Silicon Quantum-Dot Floating-Gate Flash Memory Device," IEEE Electron Device Lett., vol. 20, no. 6, pp. 286-288, 1999.

J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, "Room Temperature Operation of a Quantum-Dot Flash Memory," IEEE Electron Device Lett., vol. 18, no. 6, pp. 278-280, 1997.

B. DeSalvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandes, and B. Guillaumot, "Experimental and Theoretical Investigation of Nano-Crystal and Nitride-Trap Memory Devices," IEEE Trans.Electron Devices, vol. 48, no. 8, pp. 1789-1799, 2001.

K. Han, I. Kim, and H. Shin, "Characteristics of P-Channel Si Nano-Crystal Memory," IEEE Trans.Electron Devices, vol. 48, no. 5, pp. 874-879, 2001.

H. I. Hanafi, S. Tiwari, and I. Khan, "Fast and Long Retention-Time Nano-Crystal Memory," IEEE Trans.Electron Devices, vol. 43, no. 9, pp. 1553-1558, 1996.

Y.-C. King, T.-J. King, and C. Hu, "A Long-Refresh Dynamic/Quasi-Nonvolatile Memory Device with 2nm Tunneling Oxide," IEEE Trans.Electron Devices, vol. 20, no. 8, pp. 409-411, 1999.

X. Tang, X. Baie, J.-P. Colinge, C. Gusting, and V. Bayot, "Two-Dimensional Self-Consistent Simulation of a Triangular P-Channel SOI Nano-Flash Memory Device," IEEE Trans.Electron Devices, vol. 49, no. 8, pp. 1420-1426, 2002.

K. Nakazato, P. J. A. Piotrowicz, D. G. Hasko, H. Ahmed, and K. Itoh, "PLED - Planar Localised Electron Devices," in Proc. Intl. Electron Devices Meeting, pp. 179-182, 1997.

H. Mizuta, K. Nakazato, P. J. A. Piotrowicz, K. Itoh, T. Teshima, K. Yamaguchi, and T. Shimada, "Normally-off PLED (Planar Localised Electron Device) for Non-Volatile Memory," in Proc. Symposium on VLSI Technology, pp. 128-129, 1998.

N. Nakazato, K. Itoh, H. Mizuta, and H. Ahmed, "Silicon Stacked Tunnel Transistor for High-Speed and High-Density Random Access Memory Gain Cells," Electronics Letters, vol. 35, no. 10, pp. 848-850, 1999.

K. Nakazato, K. Itoh, H. Ahmed, H. Mizuta, T. Kisu, M. Kato, and T. Sakata, "Phase-state Low Electron-number Drive Random Access Memory (PLEDM)," in Proc. Intl. Solid-State Circuits Conf., p. TA 7.4, 2000.

H. Mizuta, M. Wagner, and K. Nakazato, "The Role of Tunnel Barriers in Phase-State Low Electron-Number Drive Transistors (PLEDTR)," IEEE Trans.Electron Devices, vol. 48, no. 6, pp. 1103-1108, 2001.

H. Fukuda, J. L. Hoyt, M. A. McCord, and R. F. W. Pease, "Fabrication of Silicon Nanopillars Containing Polycristalline Silicon/Insulator Multilayer Structures," Appl.Phys.Lett., vol. 70, no. 3, pp. 333-335, 1997.

F. Capasso, F. Beltram, R. J. Malik, and J. F. Walker, "New Floating-Gate AlGaAs/GaAs Memory Devices with Graded-Gap Electron Injector and Long Retention Times," IEEE Electron Device Lett., vol. 9, no. 8, pp. 377-379, 1988.

K. K. Likharev, "Layered Tunnel Barriers for Nonvolatile Memory Devices," Appl.Phys.Lett., vol. 73, no. 15, pp. 2137-2139, 1998.

B. Govoreanu, P. Blomme, M. Rosmeulen, J. V. Houdt, and K. D. Meyer, "VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices," IEEE Electron Device Lett., vol. 24, no. 2, pp. 99-101, 2003.

A. Gehring: Simulation of Tunneling in Semiconductor Devices