The 2D extraction procedure is described using an N-channel MOSFET. The same procedure can be applied to a P-channel device.
)
is first determined using one capacitance measurement in the accumulation
region as suggested in [87]. The polysilicon gate length (
)
and polysilicon gate concentration (
) are then extracted by matching
experimental gate-to-channel quasi-static capacitances (
) and
simulated results that take into account the polysilicon depletion effect
[42][33]. Finally, the source/drain diode
donor profile is measured directly using a 1D direct technique such as
secondary ion mass spectrometry (SIMS).
The method was applied to data collected from devices fabricated using
a retrograde n-well, salicided dual-gate CMOS process [44][43].
All experimental C-V characteristics were obtained using an HP4145B parameter
analyzer and an HP 4275A LCR meter. The measurement frequency of the HP 4275A
LCR meter was set to 100 kHz. The resolution of the system is around 0.1 fF.
In order to reduce the noise level in the measured results, the experimental
data for sub 0.5
m devices were averaged for several measurements.
As a result, the actual resolution of experimental data is better
than 0.1 fF.