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1.1 The Road to NanoTCAD

The aim of the International Technology Roadmap on Semiconductors [RO003] is to give a very detailed industrial perspective on the future requirements for micro/nano electronic technologies. The roadmap is built on a worldwide consensus of leading industrial technologists. It provides guidance for the semiconductor industry and for academic research worldwide. The goal is to continue exponential gains in performance per price for the next fifteen years.

The consensus opinion within the semiconductor industry is that CMOS scaling can be extended until some time between 2012 and 2016. The roadmap projects that by 2016, half-pitch spacing of metal lines will be 22 nanometers (``22 nm node'') and device gate lengths will be 9 nanometers. Beyond 2016, CMOS scaling will slow significantly and alternative technologies will emerge. A hypothetical 16 nm CMOS node is still speculated about. The nature of these alternative technologies is unclear, but what is clear is that the enormous silicon infrastructure will force the alternative technologies to be integrated on silicon platform and hence CMOS compatibility will play an important role in determining which of the emerging technologies becomes economically significant.

Technology Computer-Aided Design (TCAD) is one of the few enabling methodologies that can reduce development cycle times and costs. Device modeling is used for scaling studies and technology optimization; therefore, the ability to correctly represent today's performance and predict tomorrow's limitations is paramount. The key driver for accurate modeling and simulation software tools is the need to obtain knowledge and insight that will reduce development cycle times and costs.

The latest roadmap from 2003 [RO003] has a full section ``Modeling and Simulation'' devoted to TCAD and a subsection dealing with device modeling. It gives a list of difficult challenges which are treated in two groups corresponding to the projected development of technology.

The first group defines ``ultimate nanoscale CMOS simulation capability'' as the main challenge through 2010. As classical MOS devices continue to be scaled, it is important to understand possible limits to scaling from a modeling perspective. The need for the predictive simulation of non-classical CMOS devices and for more accurate solutions to the Boltzmann equation is stressed.

The second group is entitled ``nano-scale modeling''. The challenge is the development of device simulation tools for the emerging candidate technologies to complement CMOS on the long-term run beyond 2010. As traditional MOS scaling becomes less effective, nano-scale device modeling will be needed to help develop innovative MOS devices as well as to explore new device structures that may operate on different principles. Quantum transport, resonant tunneling and spintronics are explicitly mentioned.

Mapping the contents of this thesis to the roadmap we see that a lot of work is required on both topics.

In the first half of this thesis we develop a six moments model for more accurate simulation of classical carrier transport. This will not give us ``ultimate CMOS simulation capability'' but it will serve the respectable aim to replace the drift-diffusion model in an intermediate gate-lengths window of 100 to 25 nm. Currently the drift-diffusion model is still the workhorse mostly used for in-production device modeling, but at smaller gate lengths it is no longer suitable.

The second half of this thesis deals with the simulation of resonant tunneling diodes (RTDs) and the phenomenon of resonant tunneling. The RTD is one of the emerging research logic devices discussed in the roadmap. While it is doubtable if RTDs will ever play a major role in mainstream technology, the numerics behind the simulation definitely does. We compare several numerical methods for the simulation of quantum transport using the RTD as a test case.

These numerical methods will play an important role for the simulation of CMOS in the near future: In recent years a large variety of CMOS compatible new device architectures has been proposed. A promising method to suppress the short-channel effect exploits thin films. Therefore fully depleted SOI, FinFETs, and various forms of double-gate or all-around gate structures have been investigated [XRB03], [BCJP03]. For such structures and gate lengths below $ 10 \mathrm{nm}$ quantum transport models are indispensable [BAM+03], [WL02].

The ever ongoing feature size reduction in state-of-the-art technology causes a continuous need for refinement and extension of transport models used in TCAD. Two such areas of refinements are the motivation for this thesis, as is explained in the next two sections.

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R. Kosik: Numerical Challenges on the Road to NanoTCAD