2.3 Layout

After finalization of the behavioural modeling of the schematic, the design is layed out into a complex combination of masks. There are several basic building blocks of the layout. The digital library consists of predefined highly optimized (in terms of speed and area) digital cells which are connected automatically by metal interconnect layers during place and route.
Memory blocks (SRAM, DRAM, OTP or NVM) are normally placed by memory generators automatically. The most demanding building block for a designer is the analog part of a design, where linearity, accuracy, and matching of the single devices play an important role. Especially the layout of this block may have an important influence on the subsequent performance of the analog part of the design by introducing additional parasitics between the single devices in the silicon (e.g. leakage). High frequency or timing dependent applications can be strongly influenced by the RLC-network of the interconnects between the analog components. Therefore, after layout a parasitic extraction has to be performed, where the RLC-network of the interconnects is extracted from the layout and this extracted values are put into the overall schematic of the integrated circuit in an additional circuit simulation run. Finally the bonding pads are placed to provide the ports of the design, where the package bond wires are connected to. There are several different pad types:

1. Digital I/O pads: These pads are optimized for the connection to and from the digital logic. The operating voltages range from 5V down to 1.3V for low power logic.
2. Analog I/O pads: These pads take special measures to provide different voltage levels depending on the process technology [29] (e.g. for high voltage drivers analog outputs have to support higher voltages than 5V).
3. VDD and VSS pads: These pads are for the supply of the chip.

The main difference of the above types is in their ESD (electrostatic discharge) protection concept. Because the devices connected to the pad types are very different (digital cells, drivers or power buses), the ESD protection concept has to account for this independently. A special subset of the Analog I/O pads is frequently termed as RF pad which provides a reduced amount of interconnect parasitics for critical analog high frequency applications. After finalization of the layout the integrated circuit may be clustered together with other circuits, if multiple products are processed together in one batch in an MPW (multi product wafer batch). For high volume products a SDT (single die tooling) is prefered, where only one product is processed in a wafer batch. The tape out marks the transfer of the layout data to the mask shop for generation of the lithography masks for processing. The data can be transferred in different formats like CIF, GDSII, EBES, or EDIF which are described in more detail in Appendix B.