The role of packaging in semiconductor electronic applications is to protect
and preserve the performance of the semiconductor device from electrical,
mechanical, and chemical corruption or impairment. This role is becoming more
and more important as well as difficult to execute as device performance,
complexity, and functionality increase with each succeeding generation of
technology.
The design of the package has a significant effect on the electrical behavior
of an integrated circuit. The electrical representation of the package
can be described in terms of a number of formats including resistance,
inductance, and capacitance (RLC) [66]. A number of software tools are available to
generate this RLC data and map it into a format for circuit simulation
programs [67], [68].There are many programs, both commercial and university based,
available for electrical modeling of packages and interconnects. Furthermore,
the thermo-mechanical behavior of packages is getting more and more
important. The change to area-array interconnect with high I/O counts and
power dissipation has made thermal deformation an important concern for
package reliability. In addition in smart power applications the self-heating
of the big high-voltage output drivers can cause severe problems in the
thermal design of the overall IC / Package / Environment system. Finally for
high frequency applications in the GHz range, the RF/Mixed signal package
modeling has to be carried out to predict the RF behavior of the overall system
more accurately. In this application fields a careful design of the package by
using simulation is mandatory. Since package modeling is a very complex issue
for its own, and it is not scope of this work more detailed information may be
found in, e.g., [69].