SIMULATION is established as an invaluable aid for the development of processes and devices for very-large-scale-integrated circuits. This work deals with the integration and application of simulators for CMOS (Complementary Metal-Oxide-Semiconductor) development.
An interactive control and programming environment for the conceptually rigorous semiconductor technology CAD system VISTA (Viennese Integrated System for Technology CAD Applications) has been developed. This environment is called TCAD Shell and supports the supervision of simulator runs as well as the extension and programming of the system on a high level of functionality and abstraction. The concepts regarding event handling, subprocess management, coarse-grained parallelization, and distributed computing are explained.
The asynchronous subprocess execution within the VISTA TCAD Shell with multiple concurrently active subprocesses, without blocking the interpreter, and the resynchronization at subprocess termination by evaluation of so-called callback functions are conceptual advantages of VISTA.
The gain in terms of functionality and convenience of use by the integration of a simulator into the semiconductor technology CAD system is demonstrated for the device simulator MINIMOS with respect to the computation of device characteristics and extreme value search.
The part devoted to simulator application first gives an introduction to device simulation as a tool for transistor development in CMOS processes. A guide for an analysis sequence of the parameters and characteristics of the MOS transistor by simulation and comparison with measurements is given. Possible reasons with respect to simulation or technology parameters are explained, if simulation doesn't fit to measurements.
Major areas in CMOS development will be explained by concrete development tasks taken from industry cooperations: The first example is a drastically simplified fabrication process with shallow highly-doped double-wells for state-of-the-art multi-megabit dynamic memories. The effect of process variations on the electrical parameters of the MOS transistors is discussed.
The second example deals with the suppression of hot carriers in order to increase device lifetime. An LDD (Lightly-Doped Drain) structure is optimized in multiple process parameters. The predictions of simulation are well confirmed by measurements of the device lifetime of the fabricated transistors.