2.1.1 Time domain methods

The model of an 8 layer interposer PCB was simulated with the FIT method using CST STUDIO SUITE^® [10]. The interposer PCB has a size of 32mm x 32mm with layer thicknesses varying between 13mm and 21mm. Trace width is 25mm and trace to trace separation is 20mm. The key facts from the signal integrity, crosstalk simulation of the interposer listed in Table 2.1 impressively reveal the progress in the development of numerical simulation and parallel computing. However, EMC simulations of whole devices have to deal with multiple ICs on complex PCBs within sizeable enclosures and complex cabling. The FIT method of CST STUDIO SUITE^® performs a time domain simulation, where the model is exited by a time domain signal and the transients have to decay for the length of the simulated signal period. For a Gaussian shaped pulse that means vanishing model energy within the simulated signal duration. Sizeable metallic enclosures usually have resonances of a reasonably high quality. The frequency domain result is obtained by application of a FFT to the time domain simulation result and the frequency resolution of the FFT is given by the overall duration of the transformed time domain signal. Since the model energy will decrease significantly more slowly for a model with high quality resonances, a simulation time magnitudes higher than in Table 2.1 will be necessary to achieve a reasonable frequency resolution. For instance, a resolution of 1MHz at an enclosure resonance of 100MHz may require a signal duration of up to 1ms: much longer than the simulated signal duration of 300ps in Table 2.1. This will be even worse for devices with attached cables. A 3m cable in air has its first l/4 resonance at 25MHz. Assuming, due to a resonance in the model, a simulated signal time that is 10 times larger, the CPU time per signal from Table 2.1 would increase from 38h to 15 days!
However, simulations with a meshing time of 3h and a simulation time per signal of about 38h are also not suitable for an efficient EMC design process. Due to the ongoing increase in computation performance, a significant reduction in the simulation time can be expected in the future. Assuming an unlikely processor clock rate of 25GHz in 2020 versus 2GHz in 2007 according to Figure 1.3(a) and further additional performance enhancements, a reduction in the simulation time by a factor 50 from 38h to 45 minutes can be estimated. However, the model complexity will also increase in the future. That and the previously mentioned increase of simulation time from high quality enclosure resonances are not considered in this estimation of 45 minutes. Assuming the same model complexity, 45 minutes are also far too much to enable multiply simulations in an optimization process with a very high degree of freedom.

Table 2.1: Key facts of the interposer simulation carried out by [10].

Total number of nodes	594,000,000
Number of unknowns	3,564,000,000
Number of processors	20
Peak memory/processor	7.5GB
CPU meshing time	3h
Signal duration	300ps
CPU time/signal	38h

The efficiency of every time domain method, not only of the FIT method, depends heavily on the signal time duration. An accurate high frequency response requires a short time step and, thus, a large number of iterations to simulate a long signal duration. The situation is even worse for the explicit Yee's FDTD method [11], which requires a time step smaller than the time that the light needs to propagate through the smallest mesh cell, known as the CFL (Courant-Friedrichs-Levy) condition [12]. Geometric structures on a PCB demand a fine mesh, which requires a much smaller time step than would be necessary to cover the highest frequency in the simulation. Implicit FDTD methods, such as the CN-FDTD (Crank-Nicolson) or the ADI-FDTD (Alternating Directions Implicit) are a solution to avoid this restriction. However, the implicit methods require matrix inversions [13][14]. A restriction to high frequencies is also given for the finite element time domain method [15]. The previously mentioned time domain methods require a volume discretization of the simulation domain. Methods with volume meshing are suitable for inhomogeneous simulation domains. However, the simulation of free space radiation efforts to mesh a certain amount of free space surrounding the device under investigation and, additionally, the application of a matched surface condition on the boundary of the surrounding free space. This is a significant drawback for emission simulations. The partial equivalent electric circuit (PEEC) method enables a simulation based only on surface discretization and can be formulated for time and frequency domain simulations [16][17][18]. Although the PEEC method needs only surface discretization, the model size limit is significantly lower than that of the previously mentioned methods, because the PEEC method is formulated with dense matrixes. Recent publications present some numerical solutions, such as, for instance, model order reduction, to extend the PEEC model size limit [19][20][21]. However, the PEEC method is just another way of solving the electric field integral equation (EFIE) [18], and it therefore has the same limitations regarding an increase in speed, as, for instance, the method of moments (MoM). The following subsection presents recent enhancements of the MoM with the fast multipole method (FMM). It shows also restrictions, especially for the modeling of the near field region, which is relevant for dense enclosures.

C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover